Re: [PATCH 2/2] ARM: dts: mediatek: mt6572: add cache data

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect L1 instruction cache line size and sets for Cortex-A7, misrepresenting hardware topology.
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commit 7654f13f8bc1ae70f4b6b62c66fe88fc8cca8e2c
Author: Roman Vivchar <rva333@protonmail.com>

ARM: dts: mediatek: mt6572: add cache data

MediaTek mt6572 includes 32 KB I-cache and D-cache, and 256 KB L2 cache.
This commit adds information about cache size, cache line size and cache
sets to the devicetree.

> diff --git a/arch/arm/boot/dts/mediatek/mt6572.dtsi b/arch/arm/boot/dts/mediatek/mt6572.dtsi
> index fa0e5df766c20..5716505dc9e4f 100644
> --- a/arch/arm/boot/dts/mediatek/mt6572.dtsi
> +++ b/arch/arm/boot/dts/mediatek/mt6572.dtsi
> @@ -20,11 +20,34 @@ cpu@0 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a7";
>  			reg = <0x0>;
> +			i-cache-size = <32768>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;

[Severity: High]
Does this inaccurately describe the Cortex-A7 L1 instruction cache geometry?
The Cortex-A7 specification defines a fixed line length of 32 bytes and is
2-way set-associative (which would imply 512 sets for 32KB).

If the kernel uses this device tree to populate the cacheinfo sysfs interface,
won't it override hardware-probed values? Userspace applications like JIT
compilers might read this incorrect 64-byte value and use the wrong stride
for cache invalidations, potentially leading to skipped lines and the
execution of stale instructions.

> +			d-cache-size = <32768>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2>;
>  		};
>  		cpu@1 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a7";
>  			reg = <0x1>;
> +			i-cache-size = <32768>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;

[Severity: High]
Can this also cause the same incorrect 64-byte line size to be propagated
to userspace for CPU1? Updating this to a 32-byte line size and 512 sets
would correctly match the Cortex-A7 hardware topology.

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260704-6572-phase1-v1-0-61c2fe6be19c@protonmail.com?part=2