[PATCH 0/2] ARM: dts: mediatek: mt6572 DT cleanup + cache info

[PATCH 0/2] ARM: dts: mediatek: mt6572 DT cleanup + cache info

[Roman Vivchar via B4 Relay]

This series replaces legacy clock naming like uart_clk, system_clk and
rtc_clk with clk-*FREQ* equivalents. It also adds L1 and L2 cache info
to properly describe hardware.

Note that patch 1 doesn't break DT ABI. The changed clock node names
and labels are consumed only by phandles, and there are no drivers
relying on the legacy names.

As a brief heads-up, this series is a small part of an ongoing effort
to upstream mt6572 support. In my kernel tree, I have brought up clocks,
pinctrl, eMMC/microSD, cpufreq, thermal, DRM, GPU and more. I plan to
send those series in the near future.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
Roman Vivchar (2):
      ARM: dts: mediatek: mt6572: rename fixed clocks
      ARM: dts: mediatek: mt6572: add cache data

 arch/arm/boot/dts/mediatek/mt6572.dtsi | 35 ++++++++++++++++++++++++++++------
 1 file changed, 29 insertions(+), 6 deletions(-)
---
base-commit: 8cd9520d35a6c38db6567e97dd93b1f11f185dc6
change-id: 20260704-6572-phase1-014d551bf7f2

Best regards,
--  
Roman Vivchar <rva333@protonmail.com>

[PATCH 1/2] ARM: dts: mediatek: mt6572: rename fixed clocks

[Roman Vivchar via B4 Relay]

From: Roman Vivchar <rva333@protonmail.com>

Old-style naming like uart_clk, system_clk and rtc_clk doesn't actually
reflect hardware on the mt6572 SoC.

For example, uart_clk is used as parent for various parts of the SoC
like AXI bus, MMC controller, SPI, etc. While it usually shouldn't be
used as active parent, uart_clk is a wrong name. The same logic applies
to the rtc_clk, that is also used as input for MultiMedia subsystem
clock.

Therefore, rename all uart_clk, system_clk and rtc_clk to clk26m, clk13m
and clk32k to properly describe the hardware.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
 arch/arm/boot/dts/mediatek/mt6572.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/mediatek/mt6572.dtsi b/arch/arm/boot/dts/mediatek/mt6572.dtsi
index ac70f266d698..fa0e5df766c2 100644
--- a/arch/arm/boot/dts/mediatek/mt6572.dtsi
+++ b/arch/arm/boot/dts/mediatek/mt6572.dtsi
@@ -28,19 +28,19 @@ cpu@1 {
 		};
 	};
 
-	uart_clk: dummy26m {
+	clk26m: clk26m {
 		compatible = "fixed-clock";
 		clock-frequency = <26000000>;
 		#clock-cells = <0>;
 	};
 
-	system_clk: dummy13m {
+	clk13m: clk13m {
 		compatible = "fixed-clock";
 		clock-frequency = <13000000>;
 		#clock-cells = <0>;
 	};
 
-	rtc_clk: dummy32k {
+	clk32k: clk32k {
 		compatible = "fixed-clock";
 		clock-frequency = <32000>;
 		#clock-cells = <0>;
@@ -64,7 +64,7 @@ timer: timer@10008000 {
 			compatible = "mediatek,mt6572-timer", "mediatek,mt6577-timer";
 			reg = <0x10008000 0x80>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&system_clk>, <&rtc_clk>;
+			clocks = <&clk13m>, <&clk32k>;
 			clock-names = "system-clk", "rtc-clk";
 		};
 
@@ -91,7 +91,7 @@ uart0: serial@11005000 {
 			compatible = "mediatek,mt6572-uart", "mediatek,mt6577-uart";
 			reg = <0x11005000 0x400>;
 			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			clock-names = "baud";
 			status = "disabled";
 		};
@@ -100,7 +100,7 @@ uart1: serial@11006000 {
 			compatible = "mediatek,mt6572-uart", "mediatek,mt6577-uart";
 			reg = <0x11006000 0x400>;
 			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			clock-names = "baud";
 			status = "disabled";
 		};

-- 
2.54.0

[PATCH 2/2] ARM: dts: mediatek: mt6572: add cache data

[Roman Vivchar via B4 Relay]

From: Roman Vivchar <rva333@protonmail.com>

MediaTek mt6572 includes 32 KB I-cache and D-cache, and 256 KB L2 cache.

Add information about cache size, cache line size and cache sets to the
devicetree.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
 arch/arm/boot/dts/mediatek/mt6572.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/mediatek/mt6572.dtsi b/arch/arm/boot/dts/mediatek/mt6572.dtsi
index fa0e5df766c2..5716505dc9e4 100644
--- a/arch/arm/boot/dts/mediatek/mt6572.dtsi
+++ b/arch/arm/boot/dts/mediatek/mt6572.dtsi
@@ -20,11 +20,34 @@ cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x0>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
 		};
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x1>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <262144>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			cache-unified;
 		};
 	};
 

-- 
2.54.0

Re: [PATCH 2/2] ARM: dts: mediatek: mt6572: add cache data

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect L1 instruction cache line size and sets for Cortex-A7, misrepresenting hardware topology.
--

commit 7654f13f8bc1ae70f4b6b62c66fe88fc8cca8e2c
Author: Roman Vivchar <rva333@protonmail.com>

ARM: dts: mediatek: mt6572: add cache data

MediaTek mt6572 includes 32 KB I-cache and D-cache, and 256 KB L2 cache.
This commit adds information about cache size, cache line size and cache
sets to the devicetree.

> diff --git a/arch/arm/boot/dts/mediatek/mt6572.dtsi b/arch/arm/boot/dts/mediatek/mt6572.dtsi
> index fa0e5df766c20..5716505dc9e4f 100644
> --- a/arch/arm/boot/dts/mediatek/mt6572.dtsi
> +++ b/arch/arm/boot/dts/mediatek/mt6572.dtsi
> @@ -20,11 +20,34 @@ cpu@0 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a7";
>  			reg = <0x0>;
> +			i-cache-size = <32768>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;

[Severity: High]
Does this inaccurately describe the Cortex-A7 L1 instruction cache geometry?
The Cortex-A7 specification defines a fixed line length of 32 bytes and is
2-way set-associative (which would imply 512 sets for 32KB).

If the kernel uses this device tree to populate the cacheinfo sysfs interface,
won't it override hardware-probed values? Userspace applications like JIT
compilers might read this incorrect 64-byte value and use the wrong stride
for cache invalidations, potentially leading to skipped lines and the
execution of stale instructions.

> +			d-cache-size = <32768>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2>;
>  		};
>  		cpu@1 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a7";
>  			reg = <0x1>;
> +			i-cache-size = <32768>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;

[Severity: High]
Can this also cause the same incorrect 64-byte line size to be propagated
to userspace for CPU1? Updating this to a 32-byte line size and 512 sets
would correctly match the Cortex-A7 hardware topology.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260704-6572-phase1-v1-0-61c2fe6be19c@protonmail.com?part=2

Re: [PATCH 1/2] ARM: dts: mediatek: mt6572: rename fixed clocks

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Low] The fixed-clock nodes are renamed to `clk26m`, `clk13m`, and `clk32k`, which violates the preferred node naming convention in the fixed-clock DT schema.

Pre-existing issues:
- [High] The UART nodes (`uart0` and `uart1`) specify `clock-names = "baud"` but omit the required `"bus"` clock, leading to a guaranteed probe failure in the UART driver.
--

commit b76c9552213f6a611c0faa777e13268895b879c6
Author: Roman Vivchar <rva333@protonmail.com>

ARM: dts: mediatek: mt6572: rename fixed clocks

This commit renames the old-style fixed clocks uart_clk, system_clk, and
rtc_clk to clk26m, clk13m, and clk32k to better reflect the hardware.

> diff --git a/arch/arm/boot/dts/mediatek/mt6572.dtsi b/arch/arm/boot/dts/mediatek/mt6572.dtsi
> index ac70f266d698d..fa0e5df766c20 100644
> --- a/arch/arm/boot/dts/mediatek/mt6572.dtsi
> +++ b/arch/arm/boot/dts/mediatek/mt6572.dtsi
> @@ -28,19 +28,19 @@ cpu@1 {
>  		};
>  	};
>  
> -	uart_clk: dummy26m {
> +	clk26m: clk26m {

[Severity: Low]
Do these new node names violate the preferred device tree schema pattern?

According to the fixed-clock schema:

Documentation/devicetree/bindings/clock/fixed-clock.yaml:
    pattern: "^clock-([0-9]+|[a-z0-9-]+)$"

Should these nodes be named clock-26m, clock-13m, and clock-32k to pass
dtbs_check without warnings?

>  		compatible = "fixed-clock";
>  		clock-frequency = <26000000>;
>  		#clock-cells = <0>;
>  	};

[ ... ]

> @@ -91,7 +91,7 @@ uart0: serial@11005000 {
>  			compatible = "mediatek,mt6572-uart", "mediatek,mt6577-uart";
>  			reg = <0x11005000 0x400>;
>  			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
> -			clocks = <&uart_clk>;
> +			clocks = <&clk26m>;
>  			clock-names = "baud";

[Severity: High]
This is a pre-existing issue, but does providing only the baud clock
cause the UART driver probe to fail?

Looking at the 8250 driver:

drivers/tty/serial/8250/8250_mtk.c:mtk8250_probe_of() {
    ...
    data->bus_clk = devm_clk_get_enabled(&pdev->dev, "bus");
    if (IS_ERR(data->bus_clk))
        return PTR_ERR(data->bus_clk);
    ...
}

If the baud clock is present, the driver skips the legacy fallback
logic and unconditionally tries to fetch the bus clock. Since bus
is omitted from the device tree, this returns an error and aborts the probe.

Should the missing bus clock be added to these UART nodes?

>  			status = "disabled";
>  		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260704-6572-phase1-v1-0-61c2fe6be19c@protonmail.com?part=1