From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
"Joerg Roedel (AMD)" <joro@8bytes.org>
Cc: Puranam V G Tejaswi <puranam.tejaswi@oss.qualcomm.com>,
Abel Vesa <abel.vesa@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
iommu@lists.linux.dev, Akhil P Oommen <akhilpo@oss.qualcomm.com>
Subject: [PATCH 1/8] drm/msm/a6xx: Fix RBBM_CLOCK_CNTL3_TP0 value in a730_hwcg
Date: Sun, 05 Jul 2026 13:44:16 +0530 [thread overview]
Message-ID: <20260705-eliza-gpu-v1-1-c9f1354dbd29@oss.qualcomm.com> (raw)
In-Reply-To: <20260705-eliza-gpu-v1-0-c9f1354dbd29@oss.qualcomm.com>
From: Puranam V G Tejaswi <puranam.tejaswi@oss.qualcomm.com>
The RBBM_CLOCK_CNTL3_TP0 entry in a730_hwcg has bits[19:16] set to 2
(clock gating enabled for that TP0 stage). As per the latest
recommendation, clear this nibble to disable clock gating for this
particular stage.
Fixes: 9588d2f860a4 ("drm/msm/a6xx: Add A730 support")
Signed-off-by: Puranam V G Tejaswi <puranam.tejaswi@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 3e6f409d13a2..a98d550b72d0 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1199,7 +1199,7 @@ static const struct adreno_reglist a730_hwcg[] = {
{ REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
{ REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
{ REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
- { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22220222 },
{ REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
{ REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
{ REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
--
2.54.0
next prev parent reply other threads:[~2026-07-05 8:14 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-05 8:14 [PATCH 0/8] drm/msm: Support for Eliza GPU Akhil P Oommen
2026-07-05 8:14 ` Akhil P Oommen [this message]
2026-07-06 8:48 ` [PATCH 1/8] drm/msm/a6xx: Fix RBBM_CLOCK_CNTL3_TP0 value in a730_hwcg Konrad Dybcio
2026-07-05 8:14 ` [PATCH 2/8] drm/msm/a6xx: Rename GBIF_CX_CONFIG to a A6XX- variant register Akhil P Oommen
2026-07-06 8:49 ` Konrad Dybcio
2026-07-06 21:37 ` Dmitry Baryshkov
2026-07-05 8:14 ` [PATCH 3/8] drm/msm/a6xx: Add Adreno 722 support Akhil P Oommen
2026-07-06 8:59 ` Konrad Dybcio
2026-07-06 19:56 ` Akhil P Oommen
2026-07-05 8:14 ` [PATCH 4/8] dt-bindings: arm-smmu: Document GPU SMMU for Eliza SoC Akhil P Oommen
2026-07-06 6:56 ` Krzysztof Kozlowski
2026-07-05 8:14 ` [PATCH 5/8] dt-bindings: display/msm: Document Adreno 722 GPU and GMU Akhil P Oommen
2026-07-06 6:57 ` Krzysztof Kozlowski
2026-07-05 8:14 ` [PATCH 6/8] arm64: dts: qcom: eliza: Add GPU SMMU node Akhil P Oommen
2026-07-06 11:07 ` Konrad Dybcio
2026-07-06 11:08 ` Konrad Dybcio
2026-07-05 8:14 ` [PATCH 7/8] arm64: dts: qcom: eliza: Add GPU nodes Akhil P Oommen
2026-07-05 8:14 ` [PATCH 8/8] arm64: dts: qcom: eliza-mtp: Enable Adreno A722 GPU Akhil P Oommen
2026-07-06 22:23 ` Dmitry Baryshkov
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