From: sashiko-bot@kernel.org
To: "Rodrigo Alencar" <rodrigo.alencar@analog.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH v6 6/6] iio: dac: ad5686: add gain control support
Date: Sun, 05 Jul 2026 11:50:38 +0000 [thread overview]
Message-ID: <20260705115038.D8DFB1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260705-ad5686-new-features-v6-6-269594c7aae5@analog.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Setting double_scale for AD5683_REGMAP SPI devices inadvertently triggers a hardware software reset.
--
commit 4e6717d62a587bcb6ce7e79580f4db51a50f4e5d
Author: Rodrigo Alencar <rodrigo.alencar@analog.com>
iio: dac: ad5686: add gain control support
This commit adds support for gain control on AD5686 and related DACs. It
adds a double_scale flag and updates the control sync functions to configure
the GAIN pin or the internal gain control bit accordingly.
> diff --git a/drivers/iio/dac/ad5686.c b/drivers/iio/dac/ad5686.c
> index 3120e6983d9e4..9165ee07646a0 100644
> --- a/drivers/iio/dac/ad5686.c
> +++ b/drivers/iio/dac/ad5686.c
[ ... ]
> @@ -50,7 +54,8 @@ static int ad5683_control_sync(struct ad5686_state *st)
>
> return ad5686_write(st, AD5686_CMD_CONTROL_REG, 0,
> FIELD_PREP(AD5683_PD_MSK, pd_val & AD5686_PD_MSK) |
> - FIELD_PREP(AD5683_REF_BIT_MSK, st->use_internal_vref ? 0 : 1));
> + FIELD_PREP(AD5683_REF_BIT_MSK, st->use_internal_vref ? 0 : 1) |
> + FIELD_PREP(AD5683_GAIN_BIT_MSK, st->double_scale ? 1 : 0));
[Severity: High]
Could setting this gain bit inadvertently trigger a hardware software reset on
SPI devices?
AD5683_GAIN_BIT_MSK is defined as BIT(11) in ad5686.h. When this value is
passed to the SPI backend, ad5686_spi_write() unconditionally shifts all
AD5683_REGMAP values left by 4 bits:
drivers/iio/dac/ad5686-spi.c:ad5686_spi_write()
cpu_to_be32(FIELD_PREP(AD5686_CMD_MSK, cmd) |
FIELD_PREP(AD5683_DATA_MSK, val));
Since AD5683_DATA_MSK is GENMASK(19, 4), the gain bit at position 11 gets
shifted to position 15. According to the AD5683 datasheet, DB15 of the Control
Register is the Software Reset bit.
Does the SPI backend need to be adjusted so that control register writes aren't
improperly shifted?
> }
>
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260705-ad5686-new-features-v6-0-269594c7aae5@analog.com?part=6
next prev parent reply other threads:[~2026-07-05 11:50 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-05 11:38 [PATCH v6 0/6] New features for the AD5686 IIO driver Rodrigo Alencar via B4 Relay
2026-07-05 11:38 ` [PATCH v6 1/6] iio: dac: ad5686: refactor command/data macros Rodrigo Alencar via B4 Relay
2026-07-05 14:24 ` Andy Shevchenko
2026-07-05 23:09 ` Jonathan Cameron
2026-07-05 23:29 ` Jonathan Cameron
2026-07-05 11:38 ` [PATCH v6 2/6] iio: dac: ad5686: introduce sync operation Rodrigo Alencar via B4 Relay
2026-07-05 11:38 ` [PATCH v6 3/6] iio: dac: ad5686: implement new sync() op for the spi bus Rodrigo Alencar via B4 Relay
2026-07-05 11:38 ` [PATCH v6 4/6] iio: dac: ad5686: read_raw/write_raw: use guard(mutex)() Rodrigo Alencar via B4 Relay
2026-07-05 11:47 ` sashiko-bot
2026-07-05 11:39 ` [PATCH v6 5/6] iio: dac: ad5686: add triggered buffer support Rodrigo Alencar via B4 Relay
2026-07-05 11:39 ` [PATCH v6 6/6] iio: dac: ad5686: add gain control support Rodrigo Alencar via B4 Relay
2026-07-05 11:50 ` sashiko-bot [this message]
2026-07-05 23:30 ` [PATCH v6 0/6] New features for the AD5686 IIO driver Jonathan Cameron
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