Re: [PATCH 02/12] clk: rockchip: Add clock controller for the RV1106

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The CPU clock transition logic hardcodes the core divider to 1 (divide-by-2) in `pre_muxs`, which silently overwrites the safe dynamic divider calculated by the generic rockchip `clk-cpu` framework. This can cause the CPU to be severely overclocked relative to its current voltage during frequency transitions.
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commit 0a7d739f9968c86bc3a23196e252f049408102b7
Author: Simon Glass <sjg@chromium.org>

clk: rockchip: Add clock controller for the RV1106

Add the clock controller driver for the Rockchip RV1106, based on the
driver from the vendor kernel by Elaine Zhang, following the structure
of the RV1103B driver.

Link: https://github.com/LuckfoxTECH/luckfox-pico

> diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c
> new file mode 100644
> index 0000000000000..88f043f34c233
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk-rv1106.c

[ ... ]

> +#define RV1106_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg, _is_pvtpll)	\
> +{									\
> +	.prate = _prate,						\
> +	.divs = {							\
> +		RV1106_CLKSEL0(_aclk_core),				\
> +		RV1106_CLKSEL1(_pclk_dbg),				\
> +	},								\
> +	.pre_muxs = {							\
> +		RV1106_CLKSEL3(1),					\

[Severity: High]
Does this hardcoded core divider safely integrate with the generic rockchip
clk-cpu framework?

The generic rockchip_cpuclk_pre_rate_change() framework computes a safe
alt_div during frequency transitions (e.g., from 96 MHz up to 216 MHz) so
the intermediate frequency stays safely below the target rate while voltage
adjusts.

It looks like writing 1 here via RV1106_CLKSEL3(1) will clobber that
dynamically calculated alt_div, since it writes exactly to the div_core
register field. If the CPU is forced to run at GPLL/2 (e.g., ~600 MHz)
while the voltage is only provisioned for 216 MHz, could this cause system
lockups or crashes due to undervoltage during cpufreq scaling?

> +		RV1106_CLKSEL2(2),					\
> +	},								\
> +	.post_muxs = {							\
> +		RV1106_CLKSEL2(_is_pvtpll),				\
> +		RV1106_CLKSEL3(0),					\
> +	},								\
> +}

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260706195818.3906949-1-sjg@chromium.org?part=2