Re: [PATCH 1/4] arm64: dts: imx8qm-ss-dma: add lpuart4 node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly added `lpuart4` node includes a `power-domain-names` property which is undocumented in the `fsl-lpuart.yaml` device tree binding, causing a devicetree schema validation failure.
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--- Patch [1]: [PATCH 1/4] arm64: dts: imx8qm-ss-dma: add lpuart4 node ---
commit 5d53e06892d921423b269317c3426f0a50c063e7
Author: Frank Li <Frank.Li@nxp.com>

arm64: dts: imx8qm-ss-dma: add lpuart4 node
    
This commit adds the lpuart4 node for the imx8qm SoC to the imx8qm-ss-dma.dtsi
device tree source.

> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
> --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
> @@ -8,6 +8,22 @@
>  /delete-node/ &adma_pwm_lpcg;
>  
>  &dma_subsys {
> +	lpuart4: serial@5a0a0000 {
> +		compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
> +		reg = <0x5a0a0000 0x1000>;
[ ... ]
> +		assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <80000000>;
> +		power-domains = <&pd IMX_SC_R_UART_4>;
> +		power-domain-names = "uart";

[Severity: Low]
Is this power-domain-names property strictly necessary here? 

This property is undocumented in the fsl-lpuart.yaml device tree binding,
which restricts allowed properties. As a result, including it causes a
devicetree schema validation failure during dtbs_check. 

Since there is only a single power domain specified for lpuart4, the kernel
PM core handles it automatically without needing it to be explicitly named.

> +		dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
> +		dma-names = "rx","tx";
> +		status = "disabled";
> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-qm_dts-v1-0-14117a48fbdb@nxp.com?part=1