* [PATCH 1/2] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals
2026-07-07 6:00 [PATCH 0/2] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan
@ 2026-07-07 6:00 ` Varadarajan Narayanan
2026-07-07 6:21 ` sashiko-bot
2026-07-07 6:00 ` [PATCH 2/2] arm64: dts: qcom: ipq5210: Enable USB and PCIe on RDP504 Varadarajan Narayanan
1 sibling, 1 reply; 4+ messages in thread
From: Varadarajan Narayanan @ 2026-07-07 6:00 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan
Describe common IPQ5210 SoC peripherals in the base DTSI so board DTS files
can enable the hardware they use.
Add nodes for USB, PCIe, QPIC NAND/BAM, QFPROM, TSENS and thermal zones.
Also describe the CPU OPP table and CPU cooling cells needed for CPU
frequency scaling and thermal throttling.
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 616 +++++++++++++++++++++++++++++++++-
1 file changed, 610 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
index 20e8b240642c..ae28407e882b 100644
--- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
@@ -4,7 +4,9 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq5210-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq5210.h>
#include <dt-bindings/reset/qcom,ipq5210-gcc.h>
/ {
@@ -28,36 +30,48 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
};
- cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
};
- cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
};
l2_0: l2-cache {
@@ -84,6 +98,40 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2-kryo-cpu";
+ opp-shared;
+ nvmem-cells = <&cpu_speed_bin>;
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-supported-hw = <0x3>;
+ opp-microvolt = <850000>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-supported-hw = <0x3>;
+ opp-microvolt = <850000>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-supported-hw = <0x3>;
+ opp-microvolt = <850000>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-supported-hw = <0x1>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
@@ -130,6 +178,170 @@ soc@0 {
dma-ranges = <0 0 0 0 0x10 0>;
ranges = <0 0 0 0 0x10 0>;
+ qusb_phy_0: phy@7b000 {
+ compatible = "qcom,ipq5210-qusb2-phy", "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x0007b000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "cfg_ahb",
+ "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ ssphy_0: phy@7d000 {
+ compatible = "qcom,ipq5210-qmp-usb3-phy", "qcom,ipq9574-qmp-usb3-phy";
+ reg = <0x0 0x0007d000 0x0 0xa00>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&xo_board>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "usb0_pipe_clk";
+
+ status = "disabled";
+ };
+
+ pcie0_phy: phy@84000 {
+ compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy";
+ reg = <0x0 0x00084000 0x0 0x1000>;
+
+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "aux", "cfg_ahb", "pipe";
+
+ assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
+ assigned-clock-rates = <20000000>;
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie0_pipe_clk";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@f4000 {
+ compatible = "qcom,ipq5210-qmp-gen3x2-pcie-phy",
+ "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+ reg = <0x0 0x000f4000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE1_AUX_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "aux", "cfg_ahb", "pipe";
+
+ assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
+ assigned-clock-rates = <20000000>;
+
+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie1_pipe_clk";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ efuse@a4000 {
+ compatible = "qcom,ipq5210-qfprom", "qcom,qfprom";
+ reg = <0x0 0x000a4000 0x0 0x741>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_bin: cpu-speed-bin@28 {
+ reg = <0x28 0x1>;
+ bits = <0 8>;
+ };
+
+ tsens_sens11_off: s11@3dd {
+ reg = <0x3dd 0x1>;
+ bits = <4 4>;
+ };
+
+ tsens_sens12_off: s12@3de {
+ reg = <0x3de 0x1>;
+ bits = <0 4>;
+ };
+
+ tsens_sens13_off: s13@3de {
+ reg = <0x3de 0x1>;
+ bits = <4 4>;
+ };
+
+ tsens_sens14_off: s14@3e5 {
+ reg = <0x3e5 0x2>;
+ bits = <7 4>;
+ };
+
+ tsens_sens15_off: s15@3e6 {
+ reg = <0x3e6 0x1>;
+ bits = <3 4>;
+ };
+
+ tsens_mode: mode@419 {
+ reg = <0x419 0x1>;
+ bits = <0 3>;
+ };
+
+ tsens_base0: base0@419 {
+ reg = <0x419 0x2>;
+ bits = <3 10>;
+ };
+
+ tsens_base1: base1@41a {
+ reg = <0x41a 0x2>;
+ bits = <5 10>;
+ };
+ };
+
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,ipq5210-tsens", "qcom,ipq5332-tsens";
+ reg = <0x0 0x004a9000 0x0 0x1000>,
+ <0x0 0x004a8000 0x0 0x1000>;
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base0>,
+ <&tsens_base1>,
+ <&tsens_sens11_off>,
+ <&tsens_sens12_off>,
+ <&tsens_sens13_off>,
+ <&tsens_sens14_off>,
+ <&tsens_sens15_off>;
+ nvmem-cell-names = "mode",
+ "base0",
+ "base1",
+ "tsens_sens11_off",
+ "tsens_sens12_off",
+ "tsens_sens13_off",
+ "tsens_sens14_off",
+ "tsens_sens15_off";
+ interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "combined";
+ #thermal-sensor-cells = <1>;
+ #qcom,sensors = <5>;
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5210-tlmm";
reg = <0x0 0x01000000 0x0 0x300000>;
@@ -146,8 +358,8 @@ gcc: clock-controller@1800000 {
reg = <0x0 0x01800000 0x0 0x40000>;
clocks = <&xo_board>,
<&sleep_clk>,
- <0>,
- <0>,
+ <&pcie0_phy>,
+ <&pcie1_phy>,
<0>,
<0>;
#clock-cells = <1>;
@@ -205,6 +417,89 @@ sdhc: mmc@7804000 {
status = "disabled";
};
+ qpic_bam: dma-controller@7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x0 0x07984000 0x0 0x1c000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ qpic_nand: spi@79b0000 {
+ compatible = "qcom,ipq5210-snand", "qcom,ipq9574-snand";
+ reg = <0x0 0x079b0000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>,
+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
+ clock-names = "core",
+ "aon",
+ "iom";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx",
+ "rx",
+ "cmd";
+
+ status = "disabled";
+ };
+
+ usb3: usb3@8a00000 {
+ compatible = "qcom,ipq5210-dwc3", "qcom,snps-dwc3";
+ reg = <0x0 0x08a00000 0x0 0x200000>;
+
+ clocks = <&gcc GCC_CNOC_USB_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <200000000>,
+ <24000000>;
+
+ interrupts-extended = <&intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "qusb2_phy",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq";
+
+ phys = <&qusb_phy_0>,
+ <&ssphy_0>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ resets = <&gcc GCC_USB_BCR>;
+
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+
+ dr_mode = "host";
+
+ status = "disabled";
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
@@ -244,6 +539,24 @@ watchdog@b017000 {
clocks = <&sleep_clk>;
};
+ apcs_glb: mailbox@b111000 {
+ compatible = "qcom,ipq5210-apcs-apps-global",
+ "qcom,ipq6018-apcs-apps-global";
+ reg = <0x0 0x0b111000 0x0 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
+ #mbox-cells = <1>;
+ };
+
+ a53pll: clock@b116000 {
+ compatible = "qcom,ipq5210-a53pll";
+ reg = <0x0 0x0b116000 0x0 0x1000>;
+ #clock-cells = <0>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
+
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x0b120000 0x0 0x1000>;
@@ -307,6 +620,297 @@ frame@b128000 {
status = "disabled";
};
};
+
+ pcie1: pcie@50000000 {
+ compatible = "qcom,pcie-ipq5210", "qcom,pcie-ipq9574";
+ reg = <0x0 0x50000000 0x0 0xf1c>,
+ <0x0 0x50000f20 0x0 0xa8>,
+ <0x0 0x50001000 0x0 0x1000>,
+ <0x0 0x000f0000 0x0 0x3000>,
+ <0x0 0x50100000 0x0 0x1000>,
+ <0x0 0x000f6000 0x0 0x1000>;
+ reg-names = "dbi",
+ "elbi",
+ "atu",
+ "parf",
+ "config",
+ "mhi";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x0 0x0 0x50200000 0x0 0x00100000>,
+ <0x02000000 0x0 0x0 0x0 0x50300000 0x0 0x0fd00000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE1_RCHNG_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng",
+ "ahb",
+ "aux";
+
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_RESET>,
+ <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>,
+ <&gcc GCC_PCIE1_AXI_S_ARES>,
+ <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>,
+ <&gcc GCC_PCIE1_AXI_M_ARES>,
+ <&gcc GCC_PCIE1_AUX_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ interconnects = <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>,
+ <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ status = "disabled";
+
+ pcie1_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie0: pcie@70000000 {
+ compatible = "qcom,pcie-ipq5210", "qcom,pcie-ipq9574";
+ reg = <0x0 0x70000000 0x0 0xf1c>,
+ <0x0 0x70000f20 0x0 0xa8>,
+ <0x0 0x70001000 0x0 0x1000>,
+ <0x0 0x00080000 0x0 0x3000>,
+ <0x0 0x70100000 0x0 0x1000>,
+ <0x0 0x00086000 0x0 0x1000>;
+ reg-names = "dbi",
+ "elbi",
+ "atu",
+ "parf",
+ "config",
+ "mhi";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x0 0x0 0x70200000 0x0 0x00100000>,
+ <0x02000000 0x0 0x0 0x0 0x70300000 0x0 0x0fd00000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE0_RCHNG_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng",
+ "ahb",
+ "aux";
+
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_RESET>,
+ <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>,
+ <&gcc GCC_PCIE0_AXI_S_ARES>,
+ <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>,
+ <&gcc GCC_PCIE0_AXI_M_ARES>,
+ <&gcc GCC_PCIE0_AUX_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ interconnects = <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>,
+ <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ status = "disabled";
+
+ pcie0_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+ };
+
+ thermal_zones: thermal-zones {
+ ethphy-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 11>;
+
+ trips {
+ ethphy-critical {
+ temperature = <125000>;
+ hysteresis = <9000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pon-uniphy-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 12>;
+
+ trips {
+ pon-uniphy-critical {
+ temperature = <125000>;
+ hysteresis = <9000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nss-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 13>;
+
+ trips {
+ nss-top-critical {
+ temperature = <125000>;
+ hysteresis = <9000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 14>;
+
+ trips {
+ cpu-critical {
+ temperature = <120000>;
+ hysteresis = <9000>;
+ type = "critical";
+ };
+
+ cpu0_thermal_alert: cpu-passive {
+ temperature = <110000>;
+ hysteresis = <9000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_thermal_alert>;
+ /* Set maximum frequency as 816 MHz */
+ cooling-device = <&cpu0 3 3>,
+ <&cpu1 3 3>,
+ <&cpu2 3 3>,
+ <&cpu3 3 3>;
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 15>;
+
+ trips {
+ cpu-critical {
+ temperature = <120000>;
+ hysteresis = <9000>;
+ type = "critical";
+ };
+
+ cpu-passive {
+ temperature = <110000>;
+ hysteresis = <9000>;
+ type = "passive";
+ };
+ };
+ };
};
timer {
--
2.34.1
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