Re: [PATCH v2 4/7] arm64: dts: mediatek: mt8186: Add and use UART AP_DMA controller

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] GICv3 SPI interrupt trigger type misconfigured as IRQ_TYPE_LEVEL_LOW.
--

--- Patch [4]: [PATCH v2 4/7] arm64: dts: mediatek: mt8186: Add and use UART AP_DMA controller ---
commit b99bac1b2094c2b77703f91408de574bf47c0652
Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
arm64: dts: mediatek: mt8186: Add and use UART AP_DMA controller

This commit adds the AP_DMA controller node to the MT8186 device tree. It also
assigns the appropriate transmit and receive DMA channels to the three UART
controllers to increase data transfer efficiency.

> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
[ ... ]
> @@ -1142,6 +1142,22 @@ systimer: timer@10017000 {
>  			clocks = <&clk13m>;
>  		};
>  
> +		apdma: dma-controller@10200d80 {
> +			compatible = "mediatek,mt8186-uart-dma", "mediatek,mt6835-uart-dma";
> +			reg = <0 0x10200d80 0 0x80>, <0 0x10200e00 0 0x80>,
> +			      <0 0x10200e80 0 0x80>, <0 0x10200f00 0 0x80>,
> +			      <0 0x10200f80 0 0x80>, <0 0x10201000 0 0x80>;
> +			interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW 0>,
> +				     <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW 0>,
> +				     <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW 0>,
> +				     <GIC_SPI 379 IRQ_TYPE_LEVEL_LOW 0>,
> +				     <GIC_SPI 380 IRQ_TYPE_LEVEL_LOW 0>,
> +				     <GIC_SPI 381 IRQ_TYPE_LEVEL_LOW 0>;
                                                      ^^^^^^^^^^^^^^^^^^

[Severity: High]
Are active-low interrupts supported by the parent controller on this system?

These interrupts are configured as IRQ_TYPE_LEVEL_LOW, but the parent GICv3
controller natively rejects active-low SPIs.

Unlike older MediaTek systems that featured an intermediate sysirq polarity
inverter, won't the GICv3 driver return -EINVAL during request_irq() and fail
to configure the UART DMA channels?

> +			clocks = <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
> +			#dma-cells = <1>;
> +			dma-requests = <6>;
> +		};
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260707154841.198870-1-angelogioacchino.delregno@collabora.com?part=4