Re: [PATCH v2 2/4] arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Broken RGMII timings due to missing driver support for stripping PHY delays.
- [Low] Undocumented MAC-level compatible string.
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--- Patch [2]: [PATCH v2 2/4] arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board ---
commit 9b347403f48cf7cfca1e37c7a4bbf38717136eeb
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board

This commit adds the device tree for the Intel SoCFPGA Agilex5 SoCDK TSN
Config2 board variant. It enables gmac1 as a TSN port utilizing a
GMII-to-RGMII converter implemented in the FPGA fabric.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts
> new file mode 100644
> index 0000000000000..bf13ccfc1faa5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts

[ ... ]

> +&gmac1 {
> +	status = "okay";
> +	compatible = "altr,socfpga-stmmac-agilex5-tsn",

[Severity: Low]
Is this new MAC-level compatible string documented in the devicetree bindings?
It appears missing from Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml,
which would cause dtbs_check validation to fail with warnings.

> +		     "altr,socfpga-stmmac-agilex5",
> +		     "snps,dwxgmac-2.10";
> +	phy-mode = "rgmii-id";

[Severity: High]
The commit message states that the new compatible string is used so the driver
can detect the converter and strip the delay bits before configuring the PHY.

Does the dwmac-socfpga driver currently support the
altr,socfpga-stmmac-agilex5-tsn string and the associated delay-stripping
logic?

If this support isn't present in the driver yet, the driver will fall back to
altr,socfpga-stmmac-agilex5 and pass rgmii-id unmodified. Will this cause the
PHY driver to add internal delays on top of the delays already provided by the
FPGA soft IP, resulting in broken RGMII timings?

> +	phy-handle = <&emac1_phy0>;
> +	max-frame-size = <9000>;

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260707061305.27580-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2