Re: [PATCH v8 5/7] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing QREF regulators for TCSR_USB4_1_CLKREF_EN clock in Mahua descriptor table.
--

--- Patch [5]: [PATCH v8 5/7] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support ---
commit 1a2cccf8fe12339a5d989a6a9c397fb34f4adf6c
Author: Qiang Yu <qiang.yu@oss.qualcomm.com>

clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support

Mahua is based on Glymur but uses a different QREF topology, requiring
distinct regulator lists and clock descriptors for its PCIe clock
references. Add mahua-specific regulator arrays and clk descriptor table,
and use match_data to select the correct descriptor table per compatible
string at probe time.

> diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c
> index e0b545258ba4c..1791e23739ed4 100644
> --- a/drivers/clk/qcom/tcsrcc-glymur.c
> +++ b/drivers/clk/qcom/tcsrcc-glymur.c

[ ... ]

> +static const struct qcom_clk_ref_desc * const tcsr_cc_mahua_clk_descs[] = {

[ ... ]

> +	[TCSR_USB3_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> +		.name = "tcsr_usb3_1_clkref_en",
> +		.offset = 0x68,
> +		.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
> +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
> +	},
> +	[TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> +		.name = "tcsr_usb4_1_clkref_en",
> +		.offset = 0x44,
> +	},

[Severity: High]
Are regulators intentionally omitted for TCSR_USB4_1_CLKREF_EN in the Mahua
descriptor table?

If the USB PHY driver requests and enables this clock, the clock framework
will skip regulator voting because .num_regulators is 0. The clock enable
register bit will toggle, but the underlying QREF PHY block will remain
unpowered. On Qualcomm platforms, accessing unpowered PHY blocks typically
causes synchronous external aborts leading to a kernel panic.

In the Glymur configuration, this clock shared the tx0_rx5 regulators with
TCSR_PCIE_1_CLKREF_EN. In Mahua, PCIE_1 was removed but USB4_1 remains
without regulators. Should this include the appropriate regulator names and
num_regulators?

> +	[TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
> +		.name = "tcsr_usb4_2_clkref_en",
> +		.offset = 0x5c,
> +		.regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators,
> +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators),
> +	},
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260708-tcsr_qref_0708-v8-0-62c42b5fa269@oss.qualcomm.com?part=5