Re: [PATCH v5 2/5] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The revised regex pattern for `mio_clk` retains the `+` multiplier on the new numeric group, allowing unintended repeating 2-digit patterns, and still lacks the underscore required to match valid clock names.
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--- Patch [2]: [PATCH v5 2/5] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern ---
commit c70f74e0485f673c66443cff9bcebc2799e80656
Author: Michal Simek <michal.simek@amd.com>
dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern

This commit updates the clock-names regex pattern for mio_clk to restrict
the MIO index to the valid 00-77 range. It replaces the invalid character
class with an explicit alternation of two-digit values.

> diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> @@ -116,7 +116,7 @@ allOf:
>              - const: pss_alt_ref_clk
>              - const: aux_ref_clk
>              - const: gt_crx_ref_clk
> -            - pattern: "^mio_clk[00-77]+.*$"
> +            - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$"

[Severity: Medium]
Does this revised regex correctly enforce the intended clock names?

By keeping the + multiplier after the new capturing group, this pattern
appears to allow unintended repeating two-digit blocks, such as mio_clk0011,
to pass validation.

Additionally, if the hardware clock names require an underscore before the
digits (e.g., mio_clk_50), omitting the underscore means the regex expects
the digits immediately after the k. Device trees using a valid clock name
with an underscore might fail schema validation as a result.

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Sashiko AI review · https://sashiko.dev/#/patchset/cover.1783516336.git.michal.simek@amd.com?part=2