From: sashiko-bot@kernel.org
To: "Cristian Ciocaltea" <cristian.ciocaltea@collabora.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org, robh@kernel.org
Subject: Re: [PATCH v3 12/14] drm/rockchip: dw_hdmi_qp: Support 10-bit YUV422 output format
Date: Wed, 08 Jul 2026 22:13:01 +0000 [thread overview]
Message-ID: <20260708221302.266FB1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260709-dw-hdmi-qp-yuv-v3-12-a4a982a9f2e7@collabora.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] The `atomic_check` callback unconditionally mutates global driver state and configures hardware PHY, breaking DRM atomic design principles and corrupting state during `TEST_ONLY` commits.
--
--- Patch [12]: [PATCH v3 12/14] drm/rockchip: dw_hdmi_qp: Support 10-bit YUV422 output format ---
commit 4acf186e6f48344c73efb358bbf5b17c6a065aa5
Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
drm/rockchip: dw_hdmi_qp: Support 10-bit YUV422 output format
This commit adds support for 10-bit YUV422 output via the
MEDIA_BUS_FMT_UYVY10_1X20 format. It also forces 8 bpc for the HDMI PHY
configuration when YUV 4:2:2 is in use to keep the PHY PLL output aligned
with the TMDS character rate.
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
> --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
[ ... ]
> @@ -226,7 +227,14 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
> }
>
> phy_cfg.hdmi.tmds_char_rate = conn_state->hdmi.tmds_char_rate;
> - phy_cfg.hdmi.bpc = conn_state->hdmi.output_bpc;
> + /*
> + * YUV422 always transmits two 12-bit components per clock cycle,
> + * regardless of the color depth, which from a rate perspective is
> + * equivalent to three 8-bit RGB components. Force 8 bpc here to
> + * keep the PHY PLL output aligned with the TMDS character rate.
> + */
> + phy_cfg.hdmi.bpc = (s->output_mode == ROCKCHIP_OUT_MODE_YUV422 ?
> + 8 : conn_state->hdmi.output_bpc);
>
> ret = phy_configure(hdmi->phy, &phy_cfg);
> if (!ret) {
> hdmi->tmds_char_rate = conn_state->hdmi.tmds_char_rate;
[Severity: High]
This is a pre-existing issue, but does dw_hdmi_qp_rockchip_encoder_atomic_check
mutate active hardware state and global driver state during TEST_ONLY commits?
Because atomic_check callbacks are executed when userspace issues a
DRM_MODE_ATOMIC_TEST_ONLY ioctl to probe display configurations, calling
phy_configure() here could actively alter the PHY hardware under an active
display.
Additionally, modifying hdmi->tmds_char_rate mutates global driver state
even if the test commit is subsequently discarded by the kernel, potentially
corrupting the active configuration. Should these side effects be deferred to
an atomic_enable or atomic_update callback instead?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260709-dw-hdmi-qp-yuv-v3-0-a4a982a9f2e7@collabora.com?part=12
next prev parent reply other threads:[~2026-07-08 22:13 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-08 21:57 [PATCH v3 00/14] Support 10-bit YUV422 and 8/10-bit YUV420 color format on DW HDMI QP Cristian Ciocaltea
2026-07-08 21:57 ` [PATCH v3 01/14] dt-bindings: display: vop2: Add missing reset properties Cristian Ciocaltea
2026-07-08 21:57 ` [PATCH v3 02/14] drm/rockchip: vop2: Fix resource leak on vop2_enable() error path Cristian Ciocaltea
2026-07-08 22:07 ` sashiko-bot
2026-07-08 21:57 ` [PATCH v3 03/14] drm/rockchip: vop2: Balance state on atomic_enable() error paths Cristian Ciocaltea
2026-07-08 22:07 ` sashiko-bot
2026-07-08 21:57 ` [PATCH v3 04/14] drm/rockchip: vop2: Send pending event when atomic_enable() fails Cristian Ciocaltea
2026-07-08 21:57 ` [PATCH v3 05/14] drm/rockchip: vop2: Avoid division by zero when computing max_dclk Cristian Ciocaltea
2026-07-08 22:07 ` sashiko-bot
2026-07-08 21:57 ` [PATCH v3 06/14] drm/rockchip: vop2: Fix VOP2_MAX_DCLK_RATE overflow on 32-bit Cristian Ciocaltea
2026-07-08 22:06 ` sashiko-bot
2026-07-08 21:57 ` [PATCH v3 07/14] drm/rockchip: vop2: Reset AXI and DCLK to improve robustness Cristian Ciocaltea
2026-07-08 22:10 ` sashiko-bot
2026-07-08 21:57 ` [PATCH v3 08/14] drm/rockchip: vop2: Avoid DCLK source switch for 10-bit YUV422 output Cristian Ciocaltea
2026-07-08 21:57 ` [PATCH v3 09/14] drm/rockchip: vop2: Consolidate HDMI PHY PLL clock parent switch Cristian Ciocaltea
2026-07-08 21:57 ` [PATCH v3 10/14] drm/rockchip: vop2: Switch to enum vop_csc_format Cristian Ciocaltea
2026-07-08 21:57 ` [PATCH v3 11/14] drm/bridge: dw-hdmi-qp: Log resolution and refresh rate in atomic_enable() Cristian Ciocaltea
2026-07-08 21:57 ` [PATCH v3 12/14] drm/rockchip: dw_hdmi_qp: Support 10-bit YUV422 output format Cristian Ciocaltea
2026-07-08 22:13 ` sashiko-bot [this message]
2026-07-08 21:57 ` [PATCH v3 13/14] drm/rockchip: dw_hdmi_qp: Enable YUV420 " Cristian Ciocaltea
2026-07-08 22:15 ` sashiko-bot
2026-07-08 21:57 ` [PATCH v3 14/14] arm64: dts: rockchip: Add RK3588 VOP2 resets Cristian Ciocaltea
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