Re: [PATCH 3/3] ARM: dts: ixp4xx: Drop the reg-offset hack

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Removing `reg-offset = <3>` without a driver workaround or `reg-io-width = <4>` breaks big-endian serial consoles on IXP4xx.
--

--- Patch [3]: [PATCH 3/3] ARM: dts: ixp4xx: Drop the reg-offset hack ---
commit 441a4bee18082ddbc2bc878dd7fd00a516e2cc30
Author: Linus Walleij <linusw@kernel.org>

ARM: dts: ixp4xx: Drop the reg-offset hack

This commit removes the reg-offset = <3> property from the UART nodes in the
IXP4xx device tree. The commit message notes that this was a hack for big
endian support and that such workarounds should be handled in the drivers.

> diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi
> index 0adeccabd4fef..b0f98da8def47 100644
> --- a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi
> +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi
> @@ -84,11 +84,6 @@ pci@c0000000 {
>  		uart0: serial@c8000000 {
>  			compatible = "intel,xscale-uart";
>  			reg = <0xc8000000 0x1000>;
> -			/*
> -			 * The reg-offset and reg-shift is a side effect
> -			 * of running the platform in big endian mode.
> -			 */
> -			reg-offset = <3>;

[Severity: High]
Does removing this break big-endian serial consoles on IXP4xx?

Without reg-offset = <3> or a replacement like reg-io-width = <4>, the 8250
UART driver will default to 8-bit memory access at offset 0. On big endian
systems, this reads from the wrong byte lane, resulting in invalid data and
loss of the serial console.

Is the driver workaround mentioned in the commit message already in place to
handle this?

>  			reg-shift = <2>;
>  			interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
>  			clock-frequency = <14745600>;
> @@ -98,11 +93,6 @@ uart0: serial@c8000000 {
>  		uart1: serial@c8001000 {
>  			compatible = "intel,xscale-uart";
>  			reg = <0xc8001000 0x1000>;
> -			/*
> -			 * The reg-offset and reg-shift is a side effect
> -			 * of running the platform in big endian mode.
> -			 */
> -			reg-offset = <3>;

[Severity: High]
Similarly for uart1, will this cause a regression on big endian configurations
if the driver side doesn't already compensate for the missing offset?

>  			reg-shift = <2>;
>  			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
>  			clock-frequency = <14745600>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260709-ixp4xx-little-endian-v1-0-e9622d0ba9e4@kernel.org?part=3