Re: [PATCH 1/3] ARM: decompressor: always set endianess on xscale

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Unconditional execution of XScale-specific CP15 cache flush instructions causes undefined instruction crashes on ARM720T (CLPS711x) CPUs in multiplatform kernels.
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--- Patch [1]: [PATCH 1/3] ARM: decompressor: always set endianess on xscale ---
commit 1aecbc0046cda85db7fa4420cfe0c46b23cbc505
Author: Arnd Bergmann <arnd@arndb.de>

ARM: decompressor: always set endianess on xscale

This commit moves the endianness switch code into head-xscale.S to support
booting BE kernels from LE bootloaders, and vice versa. It adds a serialization
sequence to flip the B bit regardless of its original state. The commit also
notes a potential issue with the existing cache flush code on ARM720T CPUs.

> diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S
> index 20fa44d59f82d..86705c865be6d 100644
> --- a/arch/arm/boot/compressed/head-xscale.S
> +++ b/arch/arm/boot/compressed/head-xscale.S
> @@ -14,6 +14,18 @@ __XScale_start:
>  
>  		@ Preserve r8/r7 i.e. kernel entry values
>  
> +		@ set correct endianness for ixp4xx regardless of bootloader
> +		mrc p15, 0, r0, c1, c0, 0
> +#ifdef CONFIG_CPU_BIG_ENDIAN
> +		orr	r0, r0, #(1 << 7)       @ enable big endian mode
> +#else
> +		bic	r0, r0, #0x80
> +#endif
> +		mcr	p15, 0, r0, c1, c0, 0
> +		mrc     p15, 0, r0, c2, c0, 0
> +		mov	r0, r0
> +		sub	pc, pc, #4		@ flush instruction pipeline
> +
>  		@ Data cache might be active.
>  		@ Be sure to flush kernel binary out of the cache,
>  		@ whatever state it is, before it is turned off.

[Severity: High]
This isn't a bug introduced by this patch, but does this XScale-specific
cache flush sequence execute unconditionally on all CPUs in a multiplatform
build?

arch/arm/boot/compressed/head-xscale.S:__XScale_start()
    ...
    mcr p15, 0, r0, c7, c10, 4  @ drain WB
    mcr p15, 0, r0, c7, c7, 0   @ flush I & D caches
    ...

When booting a multiplatform kernel configured with both CONFIG_CPU_XSCALE and
CONFIG_CPU_ARM720T on an ARM720T CPU (such as CLPS711x), could this cause a
fatal undefined instruction exception during early boot?

Since these CP15 cache flush instructions are undefined on the ARM720T
architecture and execute before the exception vectors are set up, does this
lead to an unconditional system crash?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260709-ixp4xx-little-endian-v1-0-e9622d0ba9e4@kernel.org?part=1