Re: [RFC PATCH 10/11] arm64: dts: qcom: monaco: Move Iris IOMMUs to child nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Misuse of `iommu-addresses` in a `reserved-memory` node creates an `IOMMU_RESV_RESERVED` region that actively blocks IOVA allocations in the 0-600MB range, rather than restricting allocations to it.
--

--- Patch [10]: [RFC PATCH 10/11] arm64: dts: qcom: monaco: Move Iris IOMMUs to child nodes ---
commit 2ee0f65b225528a8b439c85350380c9a56ad101f
Author: Vikash Garodia <vikash.garodia@oss.qualcomm.com>

arm64: dts: qcom: monaco: Move Iris IOMMUs to child nodes

This commit splits the Iris VPU device into non-pixel and pixel child nodes
to accommodate different IOVA constraints. It adds a reserved IOVA range
intending to limit the non-pixel stream to the 0-600 MB range.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -831,6 +831,10 @@ video_mem: video-region@9be82000 {
>  			reg = <0x0 0x9be82000 0x0 0x700000>;
>  			no-map;
>  		};
> +
> +		iris_resv: reservation-iris {
> +			iommu-addresses = <&iris_non_pixel 0x0 0x0 0x0 0x25800000>;
> +		};

[Severity: High]
Does this iommu-addresses property block allocations in the 0-600MB range
instead of restricting allocations to it?

During device probe, of_iommu_get_resv_regions() parses this memory-region.
Because iris_resv has an iommu-addresses property but lacks a physical reg
property, it is classified as IOMMU_RESV_RESERVED.

The IOMMU DMA allocator then passes this range to reserve_iova(), which
explicitly excludes the 0-600MB range from the available IOVA pool. 

Will this force subsequent allocations for the non-pixel stream into addresses
above 600MB, resulting in the exact IOMMU faults and device crashes this
patch intends to fix?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260709-vpu_iommu_iova_handling-v1-0-72bb62cb2dfd@oss.qualcomm.com?part=10