Re: [PATCH 4/4] arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Hardcoded memory bandwidths for LPDDR5 in the SoC DTSI without accommodating LPDDR4 variants.
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--- Patch [4]: [PATCH 4/4] arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths ---
commit a003f8c1742072e3a4def9c84f16252b9b3b93fb
Author: Luca Weiss <luca.weiss@fairphone.com>

arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths

This commit adds the OPP tables for each CPU cluster to permit scaling
the DDR and L3 cache frequency. The bandwidth requests are aggregated
across CPU cores based on their current OPP configuration.

> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
[ ... ]
> +	cpu0_opp_table: opp-table-cpu0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
[ ... ]
> +		opp-1497600000 {
> +			opp-hz = /bits/ 64 <1497600000>;
> +			opp-peak-kBps = <(768000 * 4) (1363200 * 32)>;
> +		};
> +
> +		opp-1593600000 {
> +			opp-hz = /bits/ 64 <1593600000>;
> +			/* TODO: ddr4 = 1017000, ddr5 = 1555000 */
> +			opp-peak-kBps = <(1555000 * 4) (1363200 * 32)>;
> +		};

[Severity: Medium]
Will hardcoding the LPDDR5 bandwidths here in the shared SoC device tree
cause issues for boards equipped with LPDDR4 memory?

Since this explicitly sets the higher LPDDR5 values and leaves the LPDDR4
values as an unresolved TODO, could this lead to LPDDR4-equipped boards
requesting out-of-spec bandwidths?

This might result in increased power consumption or interconnect configuration
errors when LPDDR4 devices attempt to scale frequencies based on these OPPs.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com?part=4