From: sashiko-bot@kernel.org
To: "Luca Weiss" <luca.weiss@fairphone.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 3/4] arm64: dts: qcom: milos: add CPU interconnect properties
Date: Fri, 10 Jul 2026 09:37:14 +0000 [thread overview]
Message-ID: <20260710093715.175431F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260710-milos-cpu-opp-v1-3-ae7f4b09bc77@fairphone.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Adding `interconnects` properties to the CPU nodes without providing an `operating-points-v2` table causes the interconnect paths to be requested but never scaled, potentially hanging the system when sync_state drops the boot bandwidth to 0.
--
--- Patch [3]: [PATCH 3/4] arm64: dts: qcom: milos: add CPU interconnect properties ---
commit dee7f3bb2bc8dddd64b4e3fb79a167672d8b6301
Author: Luca Weiss <luca.weiss@fairphone.com>
arm64: dts: qcom: milos: add CPU interconnect properties
This commit adds the interconnect entries for each CPU. It defines two
different paths: CPU to DDR, and L3 Cache from CPU to DDR interface.
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> index 243210e6cb6eb..63dbd03512975 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
[ ... ]
> @@ -65,6 +66,11 @@ cpu0: cpu@0 {
>
> qcom,freq-domain = <&cpufreq_hw 0>;
>
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> +
[Severity: High]
Will this cause the system to hang when the interconnect driver's sync_state
callback is executed?
Since there is no operating-points-v2 table defined for the CPU nodes in this
device tree, qcom-cpufreq-hw will fail dev_pm_opp_of_add_table() with -ENODEV
and will not enable interconnect scaling.
However, because the interconnects property is present, a Device Link is
created that defers the interconnect provider's sync_state until
qcom-cpufreq-hw probes. Once it probes successfully without ever making a
bandwidth vote, sync_state will run and drop the initial boot bandwidth to 0.
Does this inadvertently throttle or disable the CPU interconnects by enforcing
a 0 vote on the CPU-to-DDR and L3 paths?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com?part=3
next prev parent reply other threads:[~2026-07-10 9:37 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-10 9:22 [PATCH 0/4] Add Milos CPU OPP table for DDR & L3 bandwidth scaling Luca Weiss
2026-07-10 9:22 ` [PATCH 1/4] dt-bindings: interconnect: OSM L3: Document Milos OSM L3 compatible Luca Weiss
2026-07-10 9:22 ` [PATCH 2/4] arm64: dts: qcom: milos: add OSM L3 node Luca Weiss
2026-07-10 13:44 ` Konrad Dybcio
2026-07-10 13:58 ` Luca Weiss
2026-07-10 14:04 ` Konrad Dybcio
2026-07-10 9:22 ` [PATCH 3/4] arm64: dts: qcom: milos: add CPU interconnect properties Luca Weiss
2026-07-10 9:37 ` sashiko-bot [this message]
2026-07-10 9:22 ` [PATCH 4/4] arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths Luca Weiss
2026-07-10 9:28 ` sashiko-bot
2026-07-10 13:45 ` Konrad Dybcio
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