[PATCH] arm64: dts: imx8mq: Add dcss node

[PATCH] arm64: dts: imx8mq: Add dcss node

[Esben Haabendal]

Add DCSS node for i.MX8MQ based on the example in the bindings
documentation.

Signed-off-by: Esben Haabendal <esben@geanix.com>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index e60872aeeb49..fb99bd3ad7c9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1611,6 +1611,27 @@ irqsteer: interrupt-controller@32e2d000 {
 			};
 		};
 
+		dcss: display-controller@32e00000 {
+			compatible = "nxp,imx8mq-dcss";
+			reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
+			interrupts = <6>, <8>, <9>;
+			interrupt-names = "ctxld", "ctxld_kick", "vblank";
+			interrupt-parent = <&irqsteer>;
+			clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+			         <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
+			         <&clk IMX8MQ_CLK_DISP_DTRC>;
+			clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+			assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
+			                  <&clk IMX8MQ_CLK_DISP_RTRM>,
+			                  <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+			                         <&clk IMX8MQ_SYS1_PLL_800M>,
+			                         <&clk IMX8MQ_CLK_27M>;
+			assigned-clock-rates = <800000000>,
+			                       <400000000>;
+			status = "disabled";
+		};
+
 		gpu: gpu@38000000 {
 			compatible = "vivante,gc";
 			reg = <0x38000000 0x40000>;

---
base-commit: 8cdeaa50eae8dad34885515f62559ee83e7e8dda
change-id: 20260710-imx8mq-dcss-device-tree-node-9df58de085ea

Best regards,
--  
Esben Haabendal <esben@geanix.com>

Re: [PATCH] arm64: dts: imx8mq: Add dcss node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The `dcss` device node is missing the `power-domains = <&pgc_disp>;` property, which will cause a bus hang when the driver accesses its registers.
- [Low] The `dcss` node is placed at the `soc` level, outside of the `aips4` bus node, causing an overlapping `reg` region and violating the hardware bus topology.
--

--- Patch [1]: [PATCH] arm64: dts: imx8mq: Add dcss node ---
commit 014c87fe4bc51f0ac006bc4660c8f156f9a40538
Author: Esben Haabendal <esben@geanix.com>

arm64: dts: imx8mq: Add dcss node
    
Add DCSS node for i.MX8MQ based on the example in the bindings documentation.

> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index e60872aeeb49e..fb99bd3ad7c92 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1611,6 +1611,27 @@ irqsteer: interrupt-controller@32e2d000 {
>  			};
>  		};
>  
> +		dcss: display-controller@32e00000 {

[Severity: Low]
The aips4 bus explicitly claims the 0x32c00000 - 0x33000000 address range:

		aips4: bus@32c00000 { /* AIPS4 */
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x32c00000 0x400000>;
			ranges = <0x32c00000 0x32c00000 0x400000>;

Placing the dcss node at the soc level with address 0x32e00000 creates an
overlapping reg region and violates the hardware bus topology, which can
cause structural devicetree warnings about overlapping ranges.

Should this node be placed as a child of the aips4 bus instead?

> +			compatible = "nxp,imx8mq-dcss";
> +			reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
> +			interrupts = <6>, <8>, <9>;

[Severity: High]
If power-domains = <&pgc_disp>; is omitted, the generic PM domain framework
won't track the dependency between this device and the DISP domain.

If no other active devices claim pgc_disp, the PM core may disable the
domain during late_initcall. 

If a board enables this node and the driver subsequently tries to access the
memory-mapped registers of the unpowered peripheral, it will trigger a
synchronous external abort and panic the kernel.

Is this node missing the power-domains property?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260710-imx8mq-dcss-device-tree-node-v1-1-fc724dfd574e@geanix.com?part=1

Re: [PATCH] arm64: dts: imx8mq: Add dcss node

[Frank Li]

On Fri, Jul 10, 2026 at 09:52:10AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] The `dcss` device node is missing the `power-domains = <&pgc_disp>;` property, which will cause a bus hang when the driver accesses its registers.
> - [Low] The `dcss` node is placed at the `soc` level, outside of the `aips4` bus node, causing an overlapping `reg` region and violating the hardware bus topology.
> --
>
> --- Patch [1]: [PATCH] arm64: dts: imx8mq: Add dcss node ---
> commit 014c87fe4bc51f0ac006bc4660c8f156f9a40538
> Author: Esben Haabendal <esben@geanix.com>
>
> arm64: dts: imx8mq: Add dcss node
>
> Add DCSS node for i.MX8MQ based on the example in the bindings documentation.
>
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index e60872aeeb49e..fb99bd3ad7c92 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -1611,6 +1611,27 @@ irqsteer: interrupt-controller@32e2d000 {
> >  			};
> >  		};
> >
> > +		dcss: display-controller@32e00000 {
>
> [Severity: Low]
> The aips4 bus explicitly claims the 0x32c00000 - 0x33000000 address range:
>
> 		aips4: bus@32c00000 { /* AIPS4 */
> 			compatible = "fsl,aips-bus", "simple-bus";
> 			reg = <0x32c00000 0x400000>;
> 			ranges = <0x32c00000 0x32c00000 0x400000>;
>
> Placing the dcss node at the soc level with address 0x32e00000 creates an
> overlapping reg region and violates the hardware bus topology, which can
> cause structural devicetree warnings about overlapping ranges.
>
> Should this node be placed as a child of the aips4 bus instead?

Make sense, please move it under aips4

Frank
>
> > +			compatible = "nxp,imx8mq-dcss";
> > +			reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
> > +			interrupts = <6>, <8>, <9>;
>
> [Severity: High]
> If power-domains = <&pgc_disp>; is omitted, the generic PM domain framework
> won't track the dependency between this device and the DISP domain.
>
> If no other active devices claim pgc_disp, the PM core may disable the
> domain during late_initcall.
>
> If a board enables this node and the driver subsequently tries to access the
> memory-mapped registers of the unpowered peripheral, it will trigger a
> synchronous external abort and panic the kernel.
>
> Is this node missing the power-domains property?
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260710-imx8mq-dcss-device-tree-node-v1-1-fc724dfd574e@geanix.com?part=1

Re: [PATCH] arm64: dts: imx8mq: Add dcss node

[Esben Haabendal]

<sashiko-bot@kernel.org> writes:

>> +			compatible = "nxp,imx8mq-dcss";
>> +			reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
>> +			interrupts = <6>, <8>, <9>;
>
> [Severity: High]
> If power-domains = <&pgc_disp>; is omitted, the generic PM domain framework
> won't track the dependency between this device and the DISP domain.
>
> If no other active devices claim pgc_disp, the PM core may disable the
> domain during late_initcall.
>
> If a board enables this node and the driver subsequently tries to access the
> memory-mapped registers of the unpowered peripheral, it will trigger a
> synchronous external abort and panic the kernel.
>
> Is this node missing the power-domains property?

As the bindings for it does not include a power-domains property, I
don't think it is missing.

/Esben

[PATCH] arm64: dts: imx8mq: add DCSS node

[Laurentiu Palcu]

This patch adds the node for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
Hi,

This is, actually, a resend of the patch because we decided to drop it
from the main DCSS patchset until the driver gets merged.

Now that the driver is in mainline, we can finally add DCSS node in DTS.

Thanks,
laurentiu

 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 5e0e7d0f1bc4..5a617f9ed8b5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1103,6 +1103,29 @@
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
 
+			dcss: display-controller@32e00000 {
+				compatible = "nxp,imx8mq-dcss";
+				reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
+				interrupts = <6>, <8>, <9>;
+				interrupt-names = "ctxld", "ctxld_kick", "vblank";
+				interrupt-parent = <&irqsteer>;
+				clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+					 <&clk IMX8MQ_VIDEO2_PLL_OUT>,
+					 <&clk IMX8MQ_CLK_DISP_DTRC>;
+				clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+				assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
+						  <&clk IMX8MQ_CLK_DISP_RTRM>,
+						  <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+							 <&clk IMX8MQ_SYS1_PLL_800M>,
+							 <&clk IMX8MQ_CLK_27M>;
+				assigned-clock-rates = <800000000>,
+						       <400000000>;
+				status = "disabled";
+			};
+
 			irqsteer: interrupt-controller@32e2d000 {
 				compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
 				reg = <0x32e2d000 0x1000>;
-- 
2.17.1

Re: [PATCH] arm64: dts: imx8mq: add DCSS node

[Lucas Stach]

On Mi, 2020-11-25 at 12:39 +0200, Laurentiu Palcu wrote:
> This patch adds the node for iMX8MQ Display Controller Subsystem.
> 
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> ---
> Hi,
> 
> This is, actually, a resend of the patch because we decided to drop it
> from the main DCSS patchset until the driver gets merged.
> 
> Now that the driver is in mainline, we can finally add DCSS node in DTS.
> 
> Thanks,
> laurentiu
> 
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 5e0e7d0f1bc4..5a617f9ed8b5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1103,6 +1103,29 @@
>  			#size-cells = <1>;
>  			ranges = <0x32c00000 0x32c00000 0x400000>;
>  
> +			dcss: display-controller@32e00000 {
> +				compatible = "nxp,imx8mq-dcss";
> +				reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
> +				interrupts = <6>, <8>, <9>;
> +				interrupt-names = "ctxld", "ctxld_kick", "vblank";
> +				interrupt-parent = <&irqsteer>;
> +				clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
> +					 <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
> +					 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
> +					 <&clk IMX8MQ_VIDEO2_PLL_OUT>,
> +					 <&clk IMX8MQ_CLK_DISP_DTRC>;
> +				clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
> +				assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
> +						  <&clk IMX8MQ_CLK_DISP_RTRM>,
> +						  <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
> +				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
> +							 <&clk IMX8MQ_SYS1_PLL_800M>,
> +							 <&clk IMX8MQ_CLK_27M>;
> +				assigned-clock-rates = <800000000>,
> +						       <400000000>;
> +				status = "disabled";
> +			};
> +
>  			irqsteer: interrupt-controller@32e2d000 {
>  				compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
>  				reg = <0x32e2d000 0x1000>;