Devicetree
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Sebastian Reichel" <sebastian.reichel@collabora.com>
Cc: olteanv@gmail.com, robh@kernel.org, conor+dt@kernel.org,
	linux-phy@lists.infradead.org, vkoul@kernel.org,
	devicetree@vger.kernel.org, neil.armstrong@linaro.org
Subject: Re: [PATCH v12 26/36] phy: rockchip: usbdp: Avoid xHCI SErrors
Date: Fri, 10 Jul 2026 21:20:27 +0000	[thread overview]
Message-ID: <20260710212027.B0FD81F00A3E@smtp.kernel.org> (raw)
In-Reply-To: <20260710-rockchip-usbdp-cleanup-v12-26-8b41a9a9bef0@collabora.com>

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [High] Clock and power leak in `rk_udphy_usb3_phy_exit` when Type-C mode drops USB support.
- [High] The patch unconditionally re-enables the SuperSpeed U3 port during PHY initialization and re-initialization, ignoring the high-speed restriction (`udphy->hs`).

Pre-existing issues:
- [High] When a Type-C device is unplugged, the PHY re-initialization is flagged but never executed, leaving the USB3 port physically disabled and breaking subsequent USB3 connections.
--

--- Patch [26]: [PATCH v12 26/36] phy: rockchip: usbdp: Avoid xHCI SErrors ---
commit 66857e87fceaec79fad3845d46dbfd48c9340977
Author: Sebastian Reichel <sebastian.reichel@collabora.com>

phy: rockchip: usbdp: Avoid xHCI SErrors

This commit addresses an SError caused by the dwc3 driver accessing xHCI
registers while the USBDP PHY is temporarily disabled during a mode switch.
It resolves this by disabling the USB3 port prior to re-initialization, which
safely re-routes the PIPE clock to the UTMI fallback clock.

> diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
> index edee27933d890..ff768e5b43ca0 100644
> --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
> +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
> @@ -1000,12 +1000,15 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
>  			rk_udphy_u3_port_disable(udphy, false);
>  		udphy->phy_needs_reinit = false;
>  	} else if (udphy->phy_needs_reinit) {
> -		if (udphy->mode == UDPHY_MODE_DP)
> -			rk_udphy_u3_port_disable(udphy, true);
> +		rk_udphy_u3_port_disable(udphy, true);
> +		udelay(10);
>  
>  		ret = rk_udphy_init(udphy);
>  		if (ret)
>  			return ret;
> +
> +		if (udphy->mode & UDPHY_MODE_USB)
> +			rk_udphy_u3_port_disable(udphy, false);

[Severity: High]
Does this code unconditionally re-enable the SuperSpeed U3 port purely based on
the mode?

During rk_udphy_usb3_phy_init(), the U3 port is kept disabled if udphy->hs is
true. However, when a mode switch or DP power-on triggers a PHY
re-initialization in rk_udphy_power_on(), this new logic executes without
checking !udphy->hs.

Could this result in misconfiguring the hardware by enabling the SuperSpeed U3
port on boards that explicitly restricted the PHY to high-speed
(maximum-speed = "high-speed")?

>  		udphy->phy_needs_reinit = false;

[Severity: High]
This is a pre-existing issue, but does the phy_needs_reinit state machine get
stuck when a Type-C device is unplugged?

If a DP-only cable is unplugged after a standard USB3 cable was active,
typec_mux_set() reverts to UDPHY_MODE_DP_USB and flags
phy_needs_reinit = true. The DP framework calls rk_udphy_dp_phy_power_off(),
which clears the DP bit from udphy->status:

drivers/phy/rockchip/phy-rockchip-usbdp.c:rk_udphy_dp_phy_power_off() {
    rk_udphy_dp_lane_enable(udphy, 0);
    rk_udphy_power_off(udphy, UDPHY_MODE_DP);
}

Because the USB3 controller never suspended, udphy->status remains non-zero
(set to UDPHY_MODE_USB), so the PHY isn't disabled. Crucially, no driver calls
rk_udphy_power_on() to process the pending phy_needs_reinit state.

Will this strand the active USB3 PHY in a disabled physical state, breaking
subsequent USB3 connections?

>  	}

[Severity: High]
Regarding the related commit in this series that clears USB status on PHY exit,
is there a clock and power leak in rk_udphy_usb3_phy_exit() when the Type-C
mode drops USB support?

In rk_udphy_usb3_phy_exit():

	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
		udphy->status &= ~UDPHY_MODE_USB;
		return 0;
	}

When the Type-C mode dynamically changes to a state without USB support (e.g.,
a DP-only cable is connected), udphy->mode becomes UDPHY_MODE_DP. If the USB
controller then suspends and calls phy_exit(), rk_udphy_usb3_phy_exit()
executes this early return.

This clears the UDPHY_MODE_USB bit from udphy->status, but misses checking if
udphy->status == UDPHY_MODE_NONE. Could this completely fail to call
rk_udphy_disable(), wasting power and potentially blocking system suspend?

Additionally, rk_udphy_power_off() inappropriately refuses to turn off active
hardware features if the negotiated Type-C udphy->mode has already shifted
away from the requested mode:

drivers/phy/rockchip/phy-rockchip-usbdp.c:rk_udphy_power_off() {
	if (!(udphy->mode & mode)) {
		dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
		return;
	}
    ...
}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260710-rockchip-usbdp-cleanup-v12-0-8b41a9a9bef0@collabora.com?part=26

  reply	other threads:[~2026-07-10 21:20 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-10 16:44 [PATCH v12 00/36] phy: rockchip: usbdp: Clean up the mess Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 01/36] dt-bindings: phy: rockchip-usbdp: add improved ports scheme Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 02/36] phy: rockchip: usbdp: Update mode_change after error handling Sebastian Reichel
2026-07-10 21:15   ` sashiko-bot
2026-07-10 16:44 ` [PATCH v12 03/36] phy: rockchip: usbdp: Do not lose USB3 PHY status Sebastian Reichel
2026-07-10 21:07   ` sashiko-bot
2026-07-10 16:44 ` [PATCH v12 04/36] phy: rockchip: usbdp: Fix devm_clk_bulk_get_all check Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 05/36] phy: rockchip: usbdp: Handle missing clock-names DT property gracefully Sebastian Reichel
2026-07-10 21:07   ` sashiko-bot
2026-07-10 16:44 ` [PATCH v12 06/36] phy: rockchip: usbdp: Drop seamless DP takeover Sebastian Reichel
2026-07-10 21:08   ` sashiko-bot
2026-07-10 16:44 ` [PATCH v12 07/36] phy: rockchip: usbdp: Keep clocks running on PHY re-init Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 08/36] phy: rockchip: usbdp: Amend SSC modulation deviation Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 09/36] phy: rockchip: usbdp: Fix LFPS detect threshold control Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 10/36] phy: rockchip: usbdp: Add missing mode_change update Sebastian Reichel
2026-07-10 21:13   ` sashiko-bot
2026-07-10 16:44 ` [PATCH v12 11/36] phy: rockchip: usbdp: Support single-lane DP Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 12/36] phy: rockchip: usbdp: Limit DP lane count to muxed lanes Sebastian Reichel
2026-07-10 21:08   ` sashiko-bot
2026-07-10 16:44 ` [PATCH v12 13/36] phy: rockchip: usbdp: Rename DP lane functions Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 14/36] phy: rockchip: usbdp: Use FIELD_PREP_WM16_CONST Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 15/36] phy: rockchip: usbdp: Cleanup DP lane selection function Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 16/36] phy: rockchip: usbdp: Register DP aux bridge Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 17/36] phy: rockchip: usbdp: Drop DP HPD handling Sebastian Reichel
2026-07-10 16:44 ` [PATCH v12 18/36] phy: rockchip: usbdp: Rename mode_change to phy_needs_reinit Sebastian Reichel
2026-07-10 21:10   ` sashiko-bot
2026-07-10 16:44 ` [PATCH v12 19/36] phy: rockchip: usbdp: Re-init the PHY on orientation change Sebastian Reichel
2026-07-10 21:15   ` sashiko-bot
2026-07-10 16:44 ` [PATCH v12 20/36] phy: rockchip: usbdp: Factor out lane_mux_sel setup Sebastian Reichel
2026-07-10 21:16   ` sashiko-bot
2026-07-10 16:44 ` [PATCH v12 21/36] phy: rockchip: usbdp: Properly handle TYPEC_STATE_SAFE and TYPEC_STATE_USB Sebastian Reichel
2026-07-10 21:18   ` sashiko-bot
2026-07-10 16:45 ` [PATCH v12 22/36] phy: rockchip: usbdp: Use guard functions for mutex Sebastian Reichel
2026-07-10 21:18   ` sashiko-bot
2026-07-10 16:45 ` [PATCH v12 23/36] phy: rockchip: usbdp: Clear USB status on PHY exit Sebastian Reichel
2026-07-10 21:17   ` sashiko-bot
2026-07-10 16:45 ` [PATCH v12 24/36] phy: rockchip: usbdp: Hold mutex in DP PHY configure Sebastian Reichel
2026-07-10 16:45 ` [PATCH v12 25/36] phy: rockchip: usbdp: Add some extra debug messages Sebastian Reichel
2026-07-10 16:45 ` [PATCH v12 26/36] phy: rockchip: usbdp: Avoid xHCI SErrors Sebastian Reichel
2026-07-10 21:20   ` sashiko-bot [this message]
2026-07-10 16:45 ` [PATCH v12 27/36] phy: rockchip: usbdp: Handle rk_udphy_reset_deassert errors Sebastian Reichel
2026-07-10 21:17   ` sashiko-bot
2026-07-10 16:45 ` [PATCH v12 28/36] phy: rockchip: usbdp: Only enable USB3 when not in high-speed mode Sebastian Reichel
2026-07-10 21:26   ` sashiko-bot
2026-07-10 16:45 ` [PATCH v12 29/36] phy: core: add notifier infrastructure Sebastian Reichel
2026-07-10 16:45 ` [PATCH v12 30/36] usb: dwc3: core: support PHY reset notifications Sebastian Reichel
2026-07-10 21:20   ` sashiko-bot
2026-07-10 16:45 ` [PATCH v12 31/36] phy: rockchip: usbdp: Add phy reset notification support Sebastian Reichel
2026-07-10 21:26   ` sashiko-bot
2026-07-10 16:45 ` [PATCH v12 32/36] phy: rockchip: usbdp: Drop -EPROBE_DEFER hack Sebastian Reichel
2026-07-10 21:28   ` sashiko-bot
2026-07-10 16:45 ` [PATCH v12 33/36] phy: rockchip: usbdp: Rename mode to hw_mode Sebastian Reichel
2026-07-10 21:23   ` sashiko-bot
2026-07-10 16:45 ` [PATCH v12 34/36] phy: rockchip: usbdp: Fix power state handling Sebastian Reichel
2026-07-10 16:45 ` [PATCH v12 35/36] phy: rockchip: usbdp: Re-init PHY on mux change Sebastian Reichel
2026-07-10 21:27   ` sashiko-bot
2026-07-10 16:45 ` [PATCH v12 36/36] phy: rockchip: usbdp: Add USB-C state without DP enabled Sebastian Reichel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260710212027.B0FD81F00A3E@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-phy@lists.infradead.org \
    --cc=neil.armstrong@linaro.org \
    --cc=olteanv@gmail.com \
    --cc=robh@kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    --cc=sebastian.reichel@collabora.com \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox