[PATCH v2 0/6] Add support for the Rockchip RV1106 and RV1103

[PATCH v2 0/6] Add support for the Rockchip RV1106 and RV1103

[Simon Glass]

This series adds initial support for the Rockchip RV1106, a Cortex-A7
SoC aimed at IP cameras, and its RV1103 package variant, together with
the Luckfox Pico Mini B, a small and widely available RV1103 board.

The series follows the structure of the recently merged RV1103B
support. The clock driver is ported from the vendor kernel and is the
work of Elaine Zhang. As with the RV1103B, no resets are exposed yet
and the CPU pvtpll is initialised but not calibrated.

Following feedback on v1, several parts have been split out into
separate series: the pinctrl driver and binding, and the serial,
watchdog and iio bindings, are submitted separately to their
maintainers. The mmc binding is already applied for mmc-next. This
series carries the clock support, the GRF compatibles and the
devicetrees, which depend on the clock binding header.

The devicetrees cover the devices needed for a basic system: UARTs,
SD/eMMC, the SPI flash controller, SARADC, watchdog, GPIO and pinctrl.

This v2 is re-tested on the Luckfox Pico Mini B: the kernel boots to
the rootfs wait with a working console on UART2, timers, pinctrl and
GPIO, and an SD card running at high speed. It builds with W=1 without
warnings and dt_binding_check and dtbs_check are clean.

Changes in v2:
- Renumber the clock IDs to be continuous, starting from 0
- Provide the MMC phase clocks from the CRU rather than a grf-cru
- Mention the MMC phase clocks in the rockchip,grf description
- Provide the MMC phase clocks from the CRU via an auxiliary GRF regmap
  rather than from a separate grf-cru clock provider
- Drop the grf-cru clock-controller child and use the syscon-only
  group for the main GRF, since the CRU now provides the MMC phase
  clocks
- Use a single gpio-ioc compatible for the per-bank IOC blocks in
  place of the ioc and pmuioc regions
- Take the MMC drive and sample phase clocks from the CRU and drop the
  grf-cru node
- Give each GPIO bank a syscon for its own IOC block, referenced by a
  rockchip,grf phandle in the bank node
- Add gpio aliases, which the pin controller and gpio drivers use to
  identify the bank; the rv1103 removes the gpio2 alias
- Split the series by subsystem: pinctrl, serial, watchdog and iio are
  now submitted separately
- Drop patch 'dt-bindings: mmc: rockchip-dw-mshc: Add RV1106
  compatible', which is applied for mmc-next

Simon Glass (6):
  dt-bindings: clock: rockchip: Add RV1106 CRU support
  clk: rockchip: Add clock controller for the RV1106
  dt-bindings: soc: rockchip: grf: Add RV1106 compatibles
  ARM: dts: rockchip: Add support for RV1106 and RV1103
  dt-bindings: arm: rockchip: Add Luckfox Pico Mini B
  ARM: dts: rockchip: Add Luckfox Pico Mini B

 .../devicetree/bindings/arm/rockchip.yaml     |    5 +
 .../bindings/clock/rockchip,rv1106-cru.yaml   |   60 +
 .../devicetree/bindings/soc/rockchip/grf.yaml |    2 +
 arch/arm/boot/dts/rockchip/Makefile           |    1 +
 .../rockchip/rv1103-luckfox-pico-mini-b.dts   |   93 ++
 arch/arm/boot/dts/rockchip/rv1103.dtsi        |   16 +
 .../arm/boot/dts/rockchip/rv1106-pinctrl.dtsi | 1398 +++++++++++++++++
 arch/arm/boot/dts/rockchip/rv1106.dtsi        |  321 ++++
 drivers/clk/rockchip/Kconfig                  |    7 +
 drivers/clk/rockchip/Makefile                 |    1 +
 drivers/clk/rockchip/clk-rv1106.c             | 1100 +++++++++++++
 .../dt-bindings/clock/rockchip,rv1106-cru.h   |  300 ++++
 12 files changed, 3304 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103-luckfox-pico-mini-b.dts
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103.dtsi
 create mode 100644 arch/arm/boot/dts/rockchip/rv1106-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/rockchip/rv1106.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rv1106.c
 create mode 100644 include/dt-bindings/clock/rockchip,rv1106-cru.h

---
base-commit: 3b029c035b34bbc693405ddf759f0e9b920c27f1
branch: rv1106a2

-- 
2.43.0

[PATCH v2 1/6] dt-bindings: clock: rockchip: Add RV1106 CRU support

[Simon Glass]

Add the clock binding header and schema for the Rockchip RV1106 clock
and reset unit. The clock IDs are numbered continuously from 0, in the
same way as the RV1103B. The header also covers the MMC drive and
sample phase clocks, which the CRU provides using control registers in
the GRF region.

The RV1103 is a package variant of the RV1106 and uses the same CRU.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Renumber the clock IDs to be continuous, starting from 0
- Provide the MMC phase clocks from the CRU rather than a grf-cru
- Mention the MMC phase clocks in the rockchip,grf description

 .../bindings/clock/rockchip,rv1106-cru.yaml   |  60 ++++
 .../dt-bindings/clock/rockchip,rv1106-cru.h   | 300 ++++++++++++++++++
 2 files changed, 360 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
 create mode 100644 include/dt-bindings/clock/rockchip,rv1106-cru.h

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
new file mode 100644
index 000000000000..b99dce9ff935
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1106-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RV1106 Clock and Reset Unit
+
+maintainers:
+  - Simon Glass <sjg@chromium.org>
+  - Heiko Stuebner <heiko@sntech.de>
+
+description:
+  The RV1106 clock controller generates the clock and also implements a
+  reset controller for SoC peripherals.
+
+properties:
+  compatible:
+    const: rockchip,rv1106-cru
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  "#reset-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: xin24m
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the syscon managing the "general register files" (GRF).
+      If missing, pll rates are not changeable due to the missing pll
+      lock status, and the MMC drive and sample phase clocks, whose
+      control registers live in the GRF region, are not registered.
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@ff3b0000 {
+      compatible = "rockchip,rv1106-cru";
+      reg = <0xff3b0000 0x20000>;
+      rockchip,grf = <&grf>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+    };
diff --git a/include/dt-bindings/clock/rockchip,rv1106-cru.h b/include/dt-bindings/clock/rockchip,rv1106-cru.h
new file mode 100644
index 000000000000..6b13e98b8d54
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rv1106-cru.h
@@ -0,0 +1,300 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
+
+/* pll clocks */
+#define PLL_APLL		0
+#define PLL_DPLL		1
+#define PLL_CPLL		2
+#define PLL_GPLL		3
+#define ARMCLK			4
+
+/* clk (clocks) */
+#define PCLK_DDRPHY		5
+#define PCLK_DDR_ROOT		6
+#define PCLK_DDRMON		7
+#define CLK_TIMER_DDRMON	8
+#define PCLK_DDRC		9
+#define PCLK_DFICTRL		10
+#define ACLK_DDR_ROOT		11
+#define ACLK_SYS_SHRM		12
+#define HCLK_NPU_ROOT		13
+#define ACLK_NPU_ROOT		14
+#define PCLK_NPU_ROOT		15
+#define HCLK_RKNN		16
+#define ACLK_RKNN		17
+#define PCLK_ACODEC		18
+#define MCLK_ACODEC_TX		19
+#define CLK_CORE_CRYPTO		20
+#define CLK_PKA_CRYPTO		21
+#define ACLK_CRYPTO		22
+#define HCLK_CRYPTO		23
+#define ACLK_DECOM		24
+#define PCLK_DECOM		25
+#define DCLK_DECOM		26
+#define ACLK_DMAC		27
+#define PCLK_DSM		28
+#define MCLK_DSM		29
+#define CCLK_SRC_EMMC		30
+#define HCLK_EMMC		31
+#define PCLK_GPIO4		32
+#define DBCLK_GPIO4		33
+#define PCLK_I2C0		34
+#define CLK_I2C0		35
+#define PCLK_I2C2		36
+#define CLK_I2C2		37
+#define PCLK_I2C3		38
+#define CLK_I2C3		39
+#define PCLK_I2C4		40
+#define CLK_I2C4		41
+#define HCLK_I2S0		42
+#define PCLK_DFT2APB		43
+#define HCLK_IVE		44
+#define ACLK_IVE		45
+#define PCLK_PWM0_PERI		46
+#define CLK_PWM0_PERI		47
+#define CLK_CAPTURE_PWM0_PERI	48
+#define PCLK_PERI_ROOT		49
+#define ACLK_PERI_ROOT		50
+#define HCLK_PERI_ROOT		51
+#define CLK_TIMER_ROOT		52
+#define ACLK_BUS_ROOT		53
+#define HCLK_SFC		54
+#define SCLK_SFC		55
+#define PCLK_UART0		56
+#define CLK_PVTM_CORE		57
+#define PCLK_UART1		58
+#define CLK_CORE_MCU_RTC	59
+#define PCLK_PWM1_PERI		60
+#define CLK_PWM1_PERI		61
+#define CLK_CAPTURE_PWM1_PERI	62
+#define PCLK_PWM2_PERI		63
+#define CLK_PWM2_PERI		64
+#define CLK_CAPTURE_PWM2_PERI	65
+#define HCLK_BOOTROM		66
+#define HCLK_SAI		67
+#define MCLK_SAI		68
+#define PCLK_SARADC		69
+#define CLK_SARADC		70
+#define PCLK_SPI1		71
+#define CLK_SPI1		72
+#define PCLK_STIMER		73
+#define CLK_STIMER0		74
+#define CLK_STIMER1		75
+#define PCLK_TIMER		76
+#define CLK_TIMER0		77
+#define CLK_TIMER1		78
+#define CLK_TIMER2		79
+#define CLK_TIMER3		80
+#define CLK_TIMER4		81
+#define CLK_TIMER5		82
+#define HCLK_TRNG_NS		83
+#define HCLK_TRNG_S		84
+#define PCLK_UART2		85
+#define HCLK_CPU		86
+#define PCLK_UART3		87
+#define CLK_CORE_MCU		88
+#define PCLK_UART4		89
+#define PCLK_DDR_HWLP		90
+#define PCLK_UART5		91
+#define ACLK_USBOTG		92
+#define CLK_REF_USBOTG		93
+#define CLK_UTMI_USBOTG		94
+#define PCLK_USBPHY		95
+#define CLK_REF_USBPHY		96
+#define PCLK_WDT_NS		97
+#define TCLK_WDT_NS		98
+#define PCLK_WDT_S		99
+#define TCLK_WDT_S		100
+#define CLK_DDR_FAIL_SAFE	101
+#define XIN_OSC0_DIV		102
+#define CLK_DEEPSLOW		103
+#define PCLK_PMU_GPIO0		104
+#define DBCLK_PMU_GPIO0		105
+#define CLK_PMU			106
+#define PCLK_PMU		107
+#define PCLK_PMU_HP_TIMER	108
+#define CLK_PMU_HP_TIMER	109
+#define CLK_PMU_32K_HP_TIMER	110
+#define PCLK_I2C1		111
+#define CLK_I2C1		112
+#define PCLK_PMU_IOC		113
+#define PCLK_PMU_MAILBOX	114
+#define CLK_PMU_MCU		115
+#define CLK_PMU_MCU_RTC		116
+#define CLK_PMU_MCU_JTAG	117
+#define CLK_PVTM_PMU		118
+#define PCLK_PVTM_PMU		119
+#define CLK_REFOUT		120
+#define CLK_100M_PMU		121
+#define PCLK_PMU_ROOT		122
+#define HCLK_PMU_ROOT		123
+#define HCLK_PMU_SRAM		124
+#define PCLK_PMU_WDT		125
+#define TCLK_PMU_WDT		126
+#define CLK_DFICTRL		127
+#define CLK_DDRMON		128
+#define CLK_DDR_PHY		129
+#define ACLK_DDRC		130
+#define CLK_CORE_DDRC_SRC	131
+#define CLK_CORE_DDRC		132
+#define CLK_50M_SRC		133
+#define CLK_100M_SRC		134
+#define CLK_150M_SRC		135
+#define CLK_200M_SRC		136
+#define CLK_250M_SRC		137
+#define CLK_300M_SRC		138
+#define CLK_339M_SRC		139
+#define CLK_400M_SRC		140
+#define CLK_450M_SRC		141
+#define CLK_500M_SRC		142
+#define CLK_I2S0_8CH_TX_SRC	143
+#define CLK_I2S0_8CH_TX_FRAC	144
+#define CLK_I2S0_8CH_TX		145
+#define CLK_I2S0_8CH_RX_SRC	146
+#define CLK_I2S0_8CH_RX_FRAC	147
+#define CLK_I2S0_8CH_RX		148
+#define I2S0_8CH_MCLKOUT	149
+#define MCLK_I2S0_8CH_RX	150
+#define MCLK_I2S0_8CH_TX	151
+#define CLK_REF_MIPI0_SRC	152
+#define CLK_REF_MIPI0_FRAC	153
+#define CLK_REF_MIPI0_OUT	154
+#define CLK_REF_MIPI1_SRC	155
+#define CLK_REF_MIPI1_FRAC	156
+#define MCLK_REF_MIPI0		157
+#define MCLK_REF_MIPI1		158
+#define CLK_REF_MIPI0		159
+#define CLK_REF_MIPI1		160
+#define CLK_UART0_SRC		161
+#define CLK_UART0_FRAC		162
+#define CLK_UART0		163
+#define SCLK_UART0		164
+#define CLK_UART1_SRC		165
+#define CLK_UART1_FRAC		166
+#define CLK_UART1		167
+#define SCLK_UART1		168
+#define CLK_UART2_SRC		169
+#define CLK_UART2_FRAC		170
+#define CLK_UART2		171
+#define SCLK_UART2		172
+#define CLK_UART3_SRC		173
+#define CLK_UART3_FRAC		174
+#define CLK_UART3		175
+#define SCLK_UART3		176
+#define CLK_UART4_SRC		177
+#define CLK_UART4_FRAC		178
+#define CLK_UART4		179
+#define SCLK_UART4		180
+#define CLK_UART5_SRC		181
+#define CLK_UART5_FRAC		182
+#define CLK_UART5		183
+#define SCLK_UART5		184
+#define CLK_VICAP_M0_SRC	185
+#define CLK_VICAP_M0_FRAC	186
+#define CLK_VICAP_M0		187
+#define SCLK_VICAP_M0		188
+#define CLK_VICAP_M1_SRC	189
+#define CLK_VICAP_M1_FRAC	190
+#define CLK_VICAP_M1		191
+#define SCLK_VICAP_M1		192
+#define DCLK_VOP_SRC		193
+#define PCLK_CRU		194
+#define PCLK_TOP_ROOT		195
+#define PCLK_SPI0		196
+#define CLK_SPI0		197
+#define SCLK_IN_SPI0		198
+#define CLK_UART_DETN_FLT	199
+#define HCLK_VEPU		200
+#define ACLK_VEPU		201
+#define CLK_CORE_VEPU		202
+#define CLK_CORE_VEPU_DVBM	203
+#define PCLK_GPIO1		204
+#define DBCLK_GPIO1		205
+#define HCLK_VEPU_PP		206
+#define ACLK_VEPU_PP		207
+#define HCLK_VEPU_ROOT		208
+#define ACLK_VEPU_COM_ROOT	209
+#define ACLK_VEPU_ROOT		210
+#define PCLK_VEPU_ROOT		211
+#define PCLK_VICAP_VEPU		212
+#define PCLK_CSIHOST0		213
+#define CLK_RXBYTECLKHS_0	214
+#define PCLK_CSIHOST1		215
+#define CLK_RXBYTECLKHS_1	216
+#define PCLK_GPIO3		217
+#define DBCLK_GPIO3		218
+#define HCLK_ISP3P2		219
+#define ACLK_ISP3P2		220
+#define CLK_CORE_ISP3P2		221
+#define PCLK_MIPICSIPHY		222
+#define CCLK_SRC_SDMMC		223
+#define HCLK_SDMMC		224
+#define CLK_SDMMC_DETN_FLT	225
+#define HCLK_VI_ROOT		226
+#define ACLK_VI_ROOT		227
+#define PCLK_VI_ROOT		228
+#define PCLK_VI_RTC_ROOT	229
+#define PCLK_VI_RTC_TEST	230
+#define PCLK_VI_RTC_PHY		231
+#define DCLK_VICAP		232
+#define PCLK_VICAP		233
+#define ACLK_VICAP		234
+#define HCLK_VICAP		235
+#define I0CLK_VICAP		236
+#define I1CLK_VICAP		237
+#define RX0PCLK_VICAP		238
+#define RX1PCLK_VICAP		239
+#define ISP0CLK_VICAP		240
+#define PCLK_GPIO2		241
+#define DBCLK_GPIO2		242
+#define ACLK_MAC		243
+#define PCLK_MAC		244
+#define CLK_GMAC0_50M_O		245
+#define CLK_GMAC0_TX_50M_O	246
+#define CLK_GMAC0_REF_50M	247
+#define CLK_GMAC0_TX_50M	248
+#define CLK_GMAC0_RX_50M	249
+#define ACLK_MAC_ROOT		250
+#define CLK_MACPHY		251
+#define CLK_OTPC_ARB		252
+#define PCLK_OTPC_NS		253
+#define CLK_SBPI_OTPC_NS	254
+#define CLK_USER_OTPC_NS	255
+#define PCLK_OTPC_S		256
+#define CLK_SBPI_OTPC_S		257
+#define CLK_USER_OTPC_S		258
+#define PCLK_OTP_MASK		259
+#define CLK_PMC_OTP		260
+#define HCLK_RGA2E		261
+#define ACLK_RGA2E		262
+#define CLK_CORE_RGA2E		263
+#define CCLK_SRC_SDIO		264
+#define HCLK_SDIO		265
+#define PCLK_TSADC		266
+#define CLK_TSADC		267
+#define CLK_TSADC_TSEN		268
+#define ACLK_VO_ROOT		269
+#define HCLK_VO_ROOT		270
+#define PCLK_VO_ROOT		271
+#define ACLK_VOP_ROOT		272
+#define HCLK_VOP		273
+#define DCLK_VOP		274
+#define ACLK_VOP		275
+#define CLK_RTC_32K		276
+#define PCLK_MAILBOX		277
+
+/* mmc phase clocks */
+#define SCLK_EMMC_DRV		278
+#define SCLK_EMMC_SAMPLE	279
+#define SCLK_SDMMC_DRV		280
+#define SCLK_SDMMC_SAMPLE	281
+#define SCLK_SDIO_DRV		282
+#define SCLK_SDIO_SAMPLE	283
+
+#endif
-- 
2.43.0

[PATCH v2 2/6] clk: rockchip: Add clock controller for the RV1106

[Simon Glass]

Add the clock and reset controller driver for the Rockchip RV1106,
based on the vendor kernel from the Luckfox Pico SDK [1] at commit
824b817f8 (a Linux 5.10.160 kernel tree), adapted to the upstream
clock framework.

The MMC drive and sample phase clocks have their control registers in
the GRF region. The CRU provides these clocks itself, using the syscon
referenced by the rockchip,grf property as an auxiliary regmap, in the
same way as the RK3528.

The RV1103 is a package variant of the RV1106 and uses the same CRU.

[1] https://github.com/LuckfoxTECH/luckfox-pico

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Provide the MMC phase clocks from the CRU via an auxiliary GRF regmap
  rather than from a separate grf-cru clock provider

 drivers/clk/rockchip/Kconfig      |    7 +
 drivers/clk/rockchip/Makefile     |    1 +
 drivers/clk/rockchip/clk-rv1106.c | 1100 +++++++++++++++++++++++++++++
 3 files changed, 1108 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk-rv1106.c

diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 85133498f013..4b55f48d72c2 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -23,6 +23,13 @@ config CLK_RV1103B
 	help
 	  Build the driver for RV1103B Clock Driver.
 
+config CLK_RV1106
+	bool "Rockchip RV1106 clock controller support"
+	depends on ARM || COMPILE_TEST
+	default y
+	help
+	  Build the driver for RV1106 Clock Driver.
+
 config CLK_RV110X
 	bool "Rockchip RV110x clock controller support"
 	depends on ARM || COMPILE_TEST
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 7c984ee006c6..554b7eb83dc9 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -19,6 +19,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
 
 obj-$(CONFIG_CLK_PX30)          += clk-px30.o
 obj-$(CONFIG_CLK_RV1103B)	+= clk-rv1103b.o
+obj-$(CONFIG_CLK_RV1106)	+= clk-rv1106.o
 obj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o
 obj-$(CONFIG_CLK_RV1126)        += clk-rv1126.o
 obj-$(CONFIG_CLK_RV1126B)	+= clk-rv1126b.o rst-rv1126b.o
diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c
new file mode 100644
index 000000000000..cb21f32c8a26
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rv1106.c
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <dt-bindings/clock/rockchip,rv1106-cru.h>
+#include "clk.h"
+
+/*
+ * Register offsets inside the CRU region. The RV1106 CRU is split into
+ * several sub-blocks, one per power domain, all accessed through a
+ * single register window.
+ */
+#define RV1106_TOPCRU_BASE		0x10000
+#define RV1106_PERICRU_BASE		0x12000
+#define RV1106_VICRU_BASE		0x14000
+#define RV1106_NPUCRU_BASE		0x16000
+#define RV1106_CORECRU_BASE		0x18000
+#define RV1106_VEPUCRU_BASE		0x1a000
+#define RV1106_VOCRU_BASE		0x1c000
+#define RV1106_DDRCRU_BASE		0x1e000
+#define RV1106_SUBDDRCRU_BASE		0x1f000
+
+#define RV1106_PMUCLKSEL_CON(x)		((x) * 0x4 + 0x300)
+#define RV1106_PMUCLKGATE_CON(x)	((x) * 0x4 + 0x800)
+#define RV1106_PLL_CON(x)		((x) * 0x4 + RV1106_TOPCRU_BASE)
+#define RV1106_MODE_CON			(0x280 + RV1106_TOPCRU_BASE)
+#define RV1106_CLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_TOPCRU_BASE)
+#define RV1106_CLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_TOPCRU_BASE)
+#define RV1106_GLB_SRST_FST		(0xc08 + RV1106_TOPCRU_BASE)
+#define RV1106_PERICLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_PERICRU_BASE)
+#define RV1106_PERICLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_PERICRU_BASE)
+#define RV1106_VICLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
+#define RV1106_VICLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
+#define RV1106_NPUCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_NPUCRU_BASE)
+#define RV1106_NPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_NPUCRU_BASE)
+#define RV1106_CORECLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_CORECRU_BASE)
+#define RV1106_CORECLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_CORECRU_BASE)
+#define RV1106_VEPUCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_VEPUCRU_BASE)
+#define RV1106_VEPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_VEPUCRU_BASE)
+#define RV1106_VOCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_VOCRU_BASE)
+#define RV1106_VOCLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_VOCRU_BASE)
+#define RV1106_DDRCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_DDRCRU_BASE)
+#define RV1106_DDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_DDRCRU_BASE)
+#define RV1106_SUBDDRCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_SUBDDRCRU_BASE)
+#define RV1106_SUBDDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_SUBDDRCRU_BASE)
+#define RV1106_SUBDDRMODE_CON		(0x280 + RV1106_SUBDDRCRU_BASE)
+
+/* Register offsets inside the GRF region for the MMC phase clocks */
+#define RV1106_VI_GRF_BASE		0x50000
+#define RV1106_VO_GRF_BASE		0x60000
+
+#define RV1106_EMMC_CON0		0x20
+#define RV1106_EMMC_CON1		0x24
+#define RV1106_SDMMC_CON0		(0x4 + RV1106_VI_GRF_BASE)
+#define RV1106_SDMMC_CON1		(0x8 + RV1106_VI_GRF_BASE)
+#define RV1106_SDIO_CON0		(0x1c + RV1106_VO_GRF_BASE)
+#define RV1106_SDIO_CON1		(0x20 + RV1106_VO_GRF_BASE)
+
+#define CRU_PVTPLL0_CON0_L		0x11000
+#define CRU_PVTPLL0_CON0_H		0x11004
+#define CRU_PVTPLL0_CON1_L		0x11008
+#define CRU_PVTPLL0_CON2_H		0x11014
+
+#define CRU_PVTPLL1_CON0_L		0x11030
+#define CRU_PVTPLL1_CON0_H		0x11034
+#define CRU_PVTPLL1_CON1_L		0x11038
+#define CRU_PVTPLL1_CON2_H		0x11044
+
+#define RV1106_GRF_SOC_STATUS0		0x10
+#define CPU_PVTPLL_CON0_L		0x40000
+#define CPU_PVTPLL_CON0_H		0x40004
+
+#define PVTPLL_RING_SEL_MASK		0x7
+#define PVTPLL_RING_SEL_SHIFT		8
+#define PVTPLL_EN_MASK			0x3
+#define PVTPLL_EN_SHIFT			0
+#define PVTPLL_LENGTH_SEL_MASK		0x7f
+#define PVTPLL_LENGTH_SEL_SHIFT		0
+
+#define CPU_CLK_PATH_BASE		RV1106_CORECLKSEL_CON(0)
+#define CPU_PVTPLL_PATH_CORE		(BIT(12) | BIT(28))
+
+#define RV1106_FRAC_MAX_PRATE		1200000000
+
+enum rv1106_plls {
+	apll, dpll, cpll, gpll,
+};
+
+static struct rockchip_pll_rate_table rv1106_pll_rates[] = {
+	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+	RK3036_PLL_RATE(993484800, 1, 124, 3, 1, 0, 3113851),
+	RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
+	RK3036_PLL_RATE(983040000, 1, 81, 2, 1, 0, 15435038),
+	RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
+	RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
+	RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+	RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
+	RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
+	RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
+	RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
+	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+	RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
+	RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
+	RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
+	RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
+	RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
+	RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
+	RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
+	RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
+	RK3036_PLL_RATE(496742400, 1, 124, 6, 1, 0, 3113851),
+	RK3036_PLL_RATE(491520000, 1, 40, 2, 1, 0, 16106127),
+	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+	RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+	{ /* sentinel */ },
+};
+
+#define RV1106_DIV_ACLK_CORE_MASK	0x1f
+#define RV1106_DIV_ACLK_CORE_SHIFT	7
+#define RV1106_DIV_PCLK_DBG_MASK	0x1f
+#define RV1106_DIV_PCLK_DBG_SHIFT	0
+#define RV1106_CORE_SEL_MASK		0x3
+#define RV1106_CORE_SEL_SHIFT		5
+#define RV1106_ALT_DIV_MASK		0x1f
+#define RV1106_ALT_DIV_SHIFT		0
+
+#define RV1106_CLKSEL0(_aclk_core)					\
+{									\
+	.reg = RV1106_CORECLKSEL_CON(0),				\
+	.val = HIWORD_UPDATE(_aclk_core, RV1106_DIV_ACLK_CORE_MASK,	\
+			     RV1106_DIV_ACLK_CORE_SHIFT),		\
+}
+
+#define RV1106_CLKSEL1(_pclk_dbg)					\
+{									\
+	.reg = RV1106_CORECLKSEL_CON(1),				\
+	.val = HIWORD_UPDATE(_pclk_dbg, RV1106_DIV_PCLK_DBG_MASK,	\
+			     RV1106_DIV_PCLK_DBG_SHIFT),		\
+}
+
+#define RV1106_CLKSEL2(_is_pvtpll)					\
+{									\
+	.reg = RV1106_CORECLKSEL_CON(0),				\
+	.val = HIWORD_UPDATE(_is_pvtpll, RV1106_CORE_SEL_MASK,		\
+			     RV1106_CORE_SEL_SHIFT),			\
+}
+
+#define RV1106_CLKSEL3(_alt_div)					\
+{									\
+	.reg = RV1106_CORECLKSEL_CON(0),				\
+	.val = HIWORD_UPDATE(_alt_div, RV1106_ALT_DIV_MASK,		\
+			     RV1106_ALT_DIV_SHIFT),			\
+}
+
+#define RV1106_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg, _is_pvtpll)	\
+{									\
+	.prate = _prate,						\
+	.divs = {							\
+		RV1106_CLKSEL0(_aclk_core),				\
+		RV1106_CLKSEL1(_pclk_dbg),				\
+	},								\
+	.pre_muxs = {							\
+		RV1106_CLKSEL3(1),					\
+		RV1106_CLKSEL2(2),					\
+	},								\
+	.post_muxs = {							\
+		RV1106_CLKSEL2(_is_pvtpll),				\
+		RV1106_CLKSEL3(0),					\
+	},								\
+}
+
+static struct rockchip_cpuclk_rate_table rv1106_cpuclk_rates[] __initdata = {
+	RV1106_CPUCLK_RATE(1608000000, 3, 7, 1),
+	RV1106_CPUCLK_RATE(1584000000, 3, 7, 1),
+	RV1106_CPUCLK_RATE(1560000000, 3, 7, 1),
+	RV1106_CPUCLK_RATE(1536000000, 3, 7, 1),
+	RV1106_CPUCLK_RATE(1512000000, 3, 7, 1),
+	RV1106_CPUCLK_RATE(1488000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1464000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1440000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1416000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1392000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1368000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1344000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1320000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1296000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1272000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1248000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1224000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1200000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1104000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1096000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1008000000, 1, 5, 1),
+	RV1106_CPUCLK_RATE(912000000, 1, 5, 1),
+	RV1106_CPUCLK_RATE(816000000, 1, 3, 1),
+	RV1106_CPUCLK_RATE(696000000, 1, 3, 0),
+	RV1106_CPUCLK_RATE(600000000, 1, 3, 0),
+	RV1106_CPUCLK_RATE(408000000, 1, 1, 0),
+	RV1106_CPUCLK_RATE(312000000, 1, 1, 0),
+	RV1106_CPUCLK_RATE(216000000,  1, 1, 0),
+	RV1106_CPUCLK_RATE(96000000, 1, 1, 0),
+};
+
+static const struct rockchip_cpuclk_reg_data rv1106_cpuclk_data = {
+	.core_reg[0] = RV1106_CORECLKSEL_CON(0),
+	.div_core_shift[0] = 0,
+	.div_core_mask[0] = 0x1f,
+	.num_cores = 1,
+	.mux_core_alt = 2,
+	.mux_core_main = 0,
+	.mux_core_shift = 5,
+	.mux_core_mask = 0x3,
+};
+
+PNAME(mux_pll_p)			= { "xin24m" };
+PNAME(mux_armclk_p)			= { "apll", "cpu_pvtpll", "gpll" };
+PNAME(mux_24m_32k_p)			= { "xin24m", "clk_rtc_32k" };
+PNAME(mux_gpll_cpll_p)			= { "gpll", "cpll" };
+PNAME(mux_gpll_24m_p)			= { "gpll", "xin24m" };
+PNAME(mux_100m_50m_24m_p)		= { "clk_100m_src", "clk_50m_src", "xin24m" };
+PNAME(mux_150m_100m_50m_24m_p)		= { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
+PNAME(mux_500m_300m_100m_24m_p)		= { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
+PNAME(mux_400m_300m_pvtpll0_pvtpll1_p)	= { "clk_400m_src", "clk_300m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
+PNAME(mux_500m_300m_pvtpll0_pvtpll1_p)	= { "clk_500m_src", "clk_300m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
+PNAME(mux_339m_200m_pvtpll0_pvtpll1_p)	= { "clk_339m_src", "clk_200m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
+PNAME(mux_400m_200m_100m_24m_p)		= { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
+PNAME(mux_200m_100m_50m_24m_p)		= { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
+PNAME(mux_300m_200m_100m_24m_p)		= { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
+PNAME(mux_500m_300m_200m_24m_p)		= { "clk_500m_src", "clk_300m_src", "clk_200m_src", "xin24m" };
+PNAME(mux_50m_24m_p)			= { "clk_50m_src", "xin24m" };
+PNAME(mux_400m_24m_p)			= { "clk_400m_src", "xin24m" };
+PNAME(clk_rtc32k_pmu_p)			= { "clk_rtc32k_frac", "xin32k", "clk_pvtm_32k" };
+PNAME(mux_200m_100m_24m_32k_p)		= { "clk_200m_src", "clk_100m_src", "xin24m", "clk_rtc_32k" };
+PNAME(mux_100m_pmu_24m_p)		= { "clk_100m_pmu", "xin24m" };
+PNAME(mux_200m_100m_24m_p)		= { "clk_200m_src", "clk_100m_pmu", "xin24m" };
+PNAME(mux_339m_200m_100m_24m_p)		= { "clk_339m_src", "clk_200m_src", "clk_100m_pmu", "xin24m" };
+PNAME(mux_dpll_300m_p)			= { "dpll", "clk_300m_src" };
+PNAME(clk_i2s0_8ch_tx_p)		= { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
+PNAME(clk_i2s0_8ch_rx_p)		= { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
+PNAME(i2s0_8ch_mclkout_p)		= { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin_osc0_half" };
+PNAME(clk_ref_mipi0_p)			= { "clk_ref_mipi0_src", "clk_ref_mipi0_frac", "xin24m" };
+PNAME(clk_ref_mipi1_p)			= { "clk_ref_mipi1_src", "clk_ref_mipi1_frac", "xin24m" };
+PNAME(clk_uart0_p)			= { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
+PNAME(clk_uart1_p)			= { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
+PNAME(clk_uart2_p)			= { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
+PNAME(clk_uart3_p)			= { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
+PNAME(clk_uart4_p)			= { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
+PNAME(clk_uart5_p)			= { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
+PNAME(clk_vicap_m0_p)			= { "clk_vicap_m0_src", "clk_vicap_m0_frac", "xin24m" };
+PNAME(clk_vicap_m1_p)			= { "clk_vicap_m1_src", "clk_vicap_m1_frac", "xin24m" };
+
+static struct rockchip_pll_clock rv1106_pll_clks[] __initdata = {
+	[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
+		     CLK_IGNORE_UNUSED, RV1106_PLL_CON(0),
+		     RV1106_MODE_CON, 0, 10, 0, rv1106_pll_rates),
+	[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
+		     0, RV1106_PLL_CON(8),
+		     RV1106_MODE_CON, 2, 10, 0, rv1106_pll_rates),
+	[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
+		     CLK_IGNORE_UNUSED, RV1106_PLL_CON(16),
+		     RV1106_SUBDDRMODE_CON, 0, 10, 0, NULL),
+	[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+		     0, RV1106_PLL_CON(24),
+		     RV1106_MODE_CON, 4, 10, 0, rv1106_pll_rates),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rv1106_rtc32k_pmu_fracmux __initdata =
+	MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+			RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_i2s0_8ch_tx_fracmux __initdata =
+	MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(19), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_i2s0_8ch_rx_fracmux __initdata =
+	MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(21), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_ref_mipi0_fracmux __initdata =
+	MUX(CLK_REF_MIPI0, "clk_ref_mipi0", clk_ref_mipi0_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(27), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_ref_mipi1_fracmux __initdata =
+	MUX(CLK_REF_MIPI1, "clk_ref_mipi1", clk_ref_mipi1_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(29), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart0_fracmux __initdata =
+	MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(7), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart1_fracmux __initdata =
+	MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(9), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart2_fracmux __initdata =
+	MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(11), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart3_fracmux __initdata =
+	MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(13), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart4_fracmux __initdata =
+	MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(15), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart5_fracmux __initdata =
+	MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(17), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_vicap_m0_fracmux __initdata =
+	MUX(CLK_VICAP_M0, "clk_vicap_m0", clk_vicap_m0_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(31), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_vicap_m1_fracmux __initdata =
+	MUX(CLK_VICAP_M1, "clk_vicap_m1", clk_vicap_m1_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(33), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
+
+	FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
+
+	/* PD_CORE */
+	GATE(CLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
+			RV1106_CORECLKGATE_CON(0), 14, GFLAGS),
+	GATE(CLK_CORE_MCU_RTC, "clk_core_mcu_rtc", "xin24m", 0,
+			RV1106_CORECLKGATE_CON(1), 6, GFLAGS),
+	COMPOSITE(HCLK_CPU, "hclk_cpu", mux_gpll_24m_p, CLK_IS_CRITICAL,
+			RV1106_CORECLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CORECLKGATE_CON(0), 12, GFLAGS),
+	COMPOSITE(CLK_CORE_MCU, "clk_core_mcu", mux_gpll_24m_p, 0,
+			RV1106_CORECLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CORECLKGATE_CON(1), 1, GFLAGS),
+	COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
+			RV1106_CORECLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
+			RV1106_CORECLKGATE_CON(0), 6, GFLAGS),
+	GATE(0, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
+			RV1106_CORECLKGATE_CON(0), 10, GFLAGS),
+	GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_cpu_root", 0,
+			RV1106_CORECLKGATE_CON(1), 8, GFLAGS),
+
+	/* PD _TOP */
+	COMPOSITE(CLK_50M_SRC, "clk_50m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE(CLK_100M_SRC, "clk_100m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 2, GFLAGS),
+	COMPOSITE(CLK_150M_SRC, "clk_150m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 3, GFLAGS),
+	COMPOSITE(CLK_200M_SRC, "clk_200m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 4, GFLAGS),
+	COMPOSITE(CLK_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 5, GFLAGS),
+	COMPOSITE(CLK_300M_SRC, "clk_300m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 6, GFLAGS),
+	COMPOSITE_HALFDIV(CLK_339M_SRC, "clk_339m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 7, GFLAGS),
+	COMPOSITE(CLK_400M_SRC, "clk_400m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 8, GFLAGS),
+	COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 9, GFLAGS),
+	COMPOSITE(CLK_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 10, GFLAGS),
+
+	COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(24), 5, 2, MFLAGS,
+			RV1106_CLKGATE_CON(2), 9, GFLAGS),
+
+	COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(17), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(1), 13, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(18), 0,
+			RV1106_CLKGATE_CON(1), 14, GFLAGS,
+			&rv1106_i2s0_8ch_tx_fracmux),
+	GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
+			RV1106_CLKGATE_CON(1), 15, GFLAGS),
+	COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(19), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(2), 0, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(20), 0,
+			RV1106_CLKGATE_CON(2), 1, GFLAGS,
+			&rv1106_i2s0_8ch_rx_fracmux),
+	GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
+			RV1106_CLKGATE_CON(2), 2, GFLAGS),
+	MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(21), 2, 2, MFLAGS),
+	COMPOSITE(CLK_REF_MIPI0_SRC, "clk_ref_mipi0_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(25), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(3), 4, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_REF_MIPI0_FRAC, "clk_ref_mipi0_frac", "clk_ref_mipi0_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(26), 0,
+			RV1106_CLKGATE_CON(3), 5, GFLAGS,
+			&rv1106_clk_ref_mipi0_fracmux),
+	GATE(MCLK_REF_MIPI0, "mclk_ref_mipi0", "clk_ref_mipi0", 0,
+			 RV1106_CLKGATE_CON(3), 6, GFLAGS),
+	COMPOSITE(CLK_REF_MIPI1_SRC, "clk_ref_mipi1_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(27), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(3), 7, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_REF_MIPI1_FRAC, "clk_ref_mipi1_frac", "clk_ref_mipi1_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(28), 0,
+			RV1106_CLKGATE_CON(3), 8, GFLAGS,
+			&rv1106_clk_ref_mipi1_fracmux),
+	GATE(MCLK_REF_MIPI1, "mclk_ref_mipi1", "clk_ref_mipi1", 0,
+			 RV1106_CLKGATE_CON(3), 9, GFLAGS),
+	COMPOSITE(CLK_UART0_SRC, "clk_uart0_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 11, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(6), 0,
+			RV1106_CLKGATE_CON(0), 12, GFLAGS,
+			&rv1106_clk_uart0_fracmux),
+	GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
+			RV1106_CLKGATE_CON(0), 13, GFLAGS),
+	COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(7), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 14, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(8), 0,
+			RV1106_CLKGATE_CON(0), 15, GFLAGS,
+			&rv1106_clk_uart1_fracmux),
+	GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
+			 RV1106_CLKGATE_CON(1), 0, GFLAGS),
+	COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(9), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(1), 1, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(10), 0,
+			RV1106_CLKGATE_CON(1), 2, GFLAGS,
+			&rv1106_clk_uart2_fracmux),
+	GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
+			 RV1106_CLKGATE_CON(1), 3, GFLAGS),
+	COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(11), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(1), 4, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(12), 0,
+			RV1106_CLKGATE_CON(1), 5, GFLAGS,
+			&rv1106_clk_uart3_fracmux),
+	GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
+			 RV1106_CLKGATE_CON(1), 6, GFLAGS),
+	COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(13), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(1), 7, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(14), 0,
+			RV1106_CLKGATE_CON(1), 8, GFLAGS,
+			&rv1106_clk_uart4_fracmux),
+	GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
+			 RV1106_CLKGATE_CON(1), 9, GFLAGS),
+	COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(15), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(1), 10, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(16), 0,
+			RV1106_CLKGATE_CON(1), 11, GFLAGS,
+			&rv1106_clk_uart5_fracmux),
+	GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
+			 RV1106_CLKGATE_CON(1), 12, GFLAGS),
+	COMPOSITE(CLK_VICAP_M0_SRC, "clk_vicap_m0_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(29), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(3), 10, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_VICAP_M0_FRAC, "clk_vicap_m0_frac", "clk_vicap_m0_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(30), 0,
+			RV1106_CLKGATE_CON(3), 11, GFLAGS,
+			&rv1106_clk_vicap_m0_fracmux),
+	GATE(SCLK_VICAP_M0, "sclk_vicap_m0", "clk_vicap_m0", 0,
+			 RV1106_CLKGATE_CON(3), 12, GFLAGS),
+	COMPOSITE(CLK_VICAP_M1_SRC, "clk_vicap_m1_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(31), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(3), 13, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_VICAP_M1_FRAC, "clk_vicap_m1_frac", "clk_vicap_m1_src", 0,
+			RV1106_CLKSEL_CON(32), 0,
+			RV1106_CLKGATE_CON(3), 14, GFLAGS,
+			&rv1106_clk_vicap_m1_fracmux),
+	GATE(SCLK_VICAP_M1, "sclk_vicap_m1", "clk_vicap_m1", 0,
+			 RV1106_CLKGATE_CON(3), 15, GFLAGS),
+	COMPOSITE(DCLK_VOP_SRC, "dclk_vop_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(23), 8, 1, MFLAGS, 3, 5, DFLAGS,
+			RV1106_CLKGATE_CON(2), 6, GFLAGS),
+
+	/* PD_DDR */
+	COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_DDRCLKSEL_CON(0), 0, 2, MFLAGS,
+			RV1106_DDRCLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_DDR_ROOT, "aclk_ddr_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_DDRCLKSEL_CON(0), 8, 2, MFLAGS,
+			RV1106_DDRCLKGATE_CON(0), 12, GFLAGS),
+	GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IGNORE_UNUSED,
+			RV1106_DDRCLKGATE_CON(1), 3, GFLAGS),
+	GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
+			RV1106_DDRCLKGATE_CON(1), 2, GFLAGS),
+	GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", 0,
+			RV1106_DDRCLKGATE_CON(0), 7, GFLAGS),
+	GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
+			RV1106_DDRCLKGATE_CON(0), 8, GFLAGS),
+	GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IGNORE_UNUSED,
+			RV1106_DDRCLKGATE_CON(0), 5, GFLAGS),
+	GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL,
+			RV1106_DDRCLKGATE_CON(0), 11, GFLAGS),
+	GATE(ACLK_SYS_SHRM, "aclk_sys_shrm", "aclk_ddr_root", CLK_IS_CRITICAL,
+			RV1106_DDRCLKGATE_CON(0), 13, GFLAGS),
+
+	/* PD_NPU */
+	COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_NPUCLKSEL_CON(0), 0, 2, MFLAGS,
+			RV1106_NPUCLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_NPU_ROOT, "aclk_npu_root", mux_500m_300m_pvtpll0_pvtpll1_p, CLK_IS_CRITICAL,
+			RV1106_NPUCLKSEL_CON(0), 2, 2, MFLAGS,
+			RV1106_NPUCLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_NPUCLKSEL_CON(0), 4, 2, MFLAGS,
+			RV1106_NPUCLKGATE_CON(0), 2, GFLAGS),
+	GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_root", 0,
+			RV1106_NPUCLKGATE_CON(0), 9, GFLAGS),
+	GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_root", 0,
+			RV1106_NPUCLKGATE_CON(0), 10, GFLAGS),
+
+	/* PD_PERI */
+	COMPOSITE_NODIV(PCLK_PERI_ROOT, "pclk_peri_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_PERICLKSEL_CON(1), 0, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_PERI_ROOT, "aclk_peri_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_PERICLKSEL_CON(1), 2, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(HCLK_PERI_ROOT, "hclk_peri_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_PERICLKSEL_CON(1), 4, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(0), 2, GFLAGS),
+	COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_PERICLKSEL_CON(9), 0, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(6), 8, GFLAGS),
+	GATE(PCLK_ACODEC, "pclk_acodec", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 3, GFLAGS),
+	COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s0_8ch_tx", 0,
+			RV1106_PERICLKSEL_CON(8), 0, 8, DFLAGS,
+			RV1106_PERICLKGATE_CON(6), 4, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_300m_200m_100m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(6), 5, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(3), 11, GFLAGS),
+	COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(6), 7, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(3), 12, GFLAGS),
+	GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus_root", 0,
+			RV1106_PERICLKGATE_CON(3), 13, GFLAGS),
+	GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 14, GFLAGS),
+	GATE(ACLK_DECOM, "aclk_decom", "aclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(5), 9, GFLAGS),
+	GATE(PCLK_DECOM, "pclk_decom", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(5), 10, GFLAGS),
+	COMPOSITE_NODIV(DCLK_DECOM, "dclk_decom", mux_400m_200m_100m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(7), 14, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(5), 11, GFLAGS),
+	GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
+			RV1106_PERICLKGATE_CON(5), 8, GFLAGS),
+	GATE(PCLK_DSM, "pclk_dsm", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 2, GFLAGS),
+	GATE(MCLK_DSM, "mclk_dsm", "mclk_i2s0_8ch_tx", 0,
+			RV1106_PERICLKGATE_CON(6), 1, GFLAGS),
+	COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_400m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(7), 6, 1, MFLAGS, 0, 6, DFLAGS,
+			RV1106_PERICLKGATE_CON(4), 12, GFLAGS),
+	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(4), 13, GFLAGS),
+	GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(2), 0, GFLAGS),
+	GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(2), 1, GFLAGS),
+	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 6, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(1), 8, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(1), 7, GFLAGS),
+	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 10, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(1), 12, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(1), 11, GFLAGS),
+	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 12, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(1), 14, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(1), 13, GFLAGS),
+	GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 14, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(2), 0, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(1), 15, GFLAGS),
+	GATE(HCLK_I2S0, "hclk_i2s0", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 0, GFLAGS),
+	GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_peri_root", CLK_IGNORE_UNUSED,
+			RV1106_PERICLKGATE_CON(6), 7, GFLAGS),
+	GATE(HCLK_IVE, "hclk_ive", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 9, GFLAGS),
+	GATE(ACLK_IVE, "aclk_ive", "aclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 10, GFLAGS),
+	GATE(PCLK_PWM0_PERI, "pclk_pwm0_peri", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(7), 3, GFLAGS),
+	COMPOSITE_NODIV(CLK_PWM0_PERI, "clk_pwm0_peri", mux_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(11), 0, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(7), 4, GFLAGS),
+	GATE(CLK_CAPTURE_PWM0_PERI, "clk_capture_pwm0_peri", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(7), 5, GFLAGS),
+	GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(0), 3, GFLAGS),
+	GATE(HCLK_SFC, "hclk_sfc", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(4), 14, GFLAGS),
+	COMPOSITE(SCLK_SFC, "sclk_sfc", mux_500m_300m_200m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(7), 12, 2, MFLAGS, 7, 5, DFLAGS,
+			RV1106_PERICLKGATE_CON(5), 0, GFLAGS),
+	GATE(PCLK_UART0, "pclk_uart0", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 11, GFLAGS),
+	GATE(PCLK_UART1, "pclk_uart1", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 15, GFLAGS),
+	GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 15, GFLAGS),
+	COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(6), 9, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(4), 0, GFLAGS),
+	GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(4), 1, GFLAGS),
+	GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(4), 2, GFLAGS),
+	COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(6), 11, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(4), 3, GFLAGS),
+	GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(4), 4, GFLAGS),
+	GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(0), 7, GFLAGS),
+	GATE(HCLK_SAI, "hclk_sai", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(5), 13, GFLAGS),
+	GATE(MCLK_SAI, "mclk_sai", "mclk_i2s0_8ch_tx", 0,
+			RV1106_PERICLKGATE_CON(5), 14, GFLAGS),
+	GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 3, GFLAGS),
+	COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
+			RV1106_PERICLKSEL_CON(6), 0, 3, DFLAGS,
+			RV1106_PERICLKGATE_CON(3), 4, GFLAGS),
+	GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 6, GFLAGS),
+	COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(6), 3, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(3), 7, GFLAGS),
+	GATE(PCLK_STIMER, "pclk_stimer", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(0), 15, GFLAGS),
+	GATE(CLK_STIMER0, "clk_stimer0", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(1), 0, GFLAGS),
+	GATE(CLK_STIMER1, "clk_stimer1", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(1), 1, GFLAGS),
+	GATE(PCLK_TIMER, "pclk_timer", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(0), 8, GFLAGS),
+	GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 9, GFLAGS),
+	GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 10, GFLAGS),
+	GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 11, GFLAGS),
+	GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 12, GFLAGS),
+	GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 13, GFLAGS),
+	GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 14, GFLAGS),
+	GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 9, GFLAGS),
+	GATE(HCLK_TRNG_S, "hclk_trng_s", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 10, GFLAGS),
+	GATE(PCLK_UART2, "pclk_uart2", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(2), 3, GFLAGS),
+	GATE(PCLK_UART3, "pclk_uart3", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(2), 7, GFLAGS),
+	GATE(PCLK_UART4, "pclk_uart4", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(2), 11, GFLAGS),
+	GATE(PCLK_UART5, "pclk_uart5", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(2), 15, GFLAGS),
+	GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_bus_root", 0,
+			RV1106_PERICLKGATE_CON(4), 7, GFLAGS),
+	GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(4), 8, GFLAGS),
+	GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(5), 1, GFLAGS),
+	GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(5), 2, GFLAGS),
+	GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 2, GFLAGS),
+	GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(1), 3, GFLAGS),
+	GATE(PCLK_WDT_S, "pclk_wdt_s", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 4, GFLAGS),
+	GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(1), 5, GFLAGS),
+
+	/* PD_PMU */
+	COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
+			RV1106_PMUCLKSEL_CON(6), 0,
+			RV1106_PMUCLKGATE_CON(1), 14, GFLAGS,
+			&rv1106_rtc32k_pmu_fracmux),
+	DIV(CLK_100M_PMU, "clk_100m_pmu", "clk_200m_src", 0,
+			RV1106_PMUCLKSEL_CON(0), 0, 3, DFLAGS),
+	COMPOSITE_NODIV(PCLK_PMU_ROOT, "pclk_pmu_root", mux_100m_pmu_24m_p, CLK_IS_CRITICAL,
+			RV1106_PMUCLKSEL_CON(0), 3, 1, MFLAGS,
+			RV1106_PMUCLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(HCLK_PMU_ROOT, "hclk_pmu_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_PMUCLKSEL_CON(0), 4, 2, MFLAGS,
+			RV1106_PMUCLKGATE_CON(0), 2, GFLAGS),
+	GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL,
+			RV1106_PMUCLKGATE_CON(1), 0, GFLAGS),
+	GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
+			RV1106_PMUCLKGATE_CON(1), 1, GFLAGS),
+	GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu", 0,
+			RV1106_PMUCLKGATE_CON(1), 15, GFLAGS),
+	GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "pclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(1), 2, GFLAGS),
+	COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", mux_24m_32k_p, 0,
+			RV1106_PMUCLKSEL_CON(0), 15, 1, MFLAGS,
+			RV1106_PMUCLKGATE_CON(1), 3, GFLAGS),
+	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(0), 3, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_24m_32k_p, 0,
+			RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS,
+			RV1106_PMUCLKGATE_CON(0), 4, GFLAGS),
+	GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(2), 10, GFLAGS),
+	GATE(CLK_PMU_MCU, "clk_pmu_mcu", "hclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(0), 9, GFLAGS),
+	GATE(CLK_PMU_MCU_RTC, "clk_pmu_mcu_rtc", "xin24m", 0,
+			RV1106_PMUCLKGATE_CON(0), 13, GFLAGS),
+	COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
+			RV1106_PMUCLKSEL_CON(1), 0, 5, DFLAGS,
+			RV1106_PMUCLKGATE_CON(1), 4, GFLAGS),
+	GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(1), 5, GFLAGS),
+	GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
+			RV1106_PMUCLKGATE_CON(2), 13, GFLAGS),
+	GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IGNORE_UNUSED,
+			RV1106_PMUCLKGATE_CON(0), 8, GFLAGS),
+	GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(2), 8, GFLAGS),
+	COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0,
+			RV1106_PMUCLKSEL_CON(7), 2, 1, MFLAGS,
+			RV1106_PMUCLKGATE_CON(2), 9, GFLAGS),
+
+	/* PD_SUBDDR */
+	COMPOSITE(CLK_CORE_DDRC_SRC, "clk_core_ddrc_src", mux_dpll_300m_p, CLK_IGNORE_UNUSED,
+			RV1106_SUBDDRCLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_SUBDDRCLKGATE_CON(0), 2, GFLAGS),
+	GATE(CLK_DFICTRL, "clk_dfictrl", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
+			RV1106_SUBDDRCLKGATE_CON(0), 5, GFLAGS),
+	GATE(CLK_DDRMON, "clk_ddrmon", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
+			RV1106_SUBDDRCLKGATE_CON(0), 4, GFLAGS),
+	GATE(CLK_DDR_PHY, "clk_ddr_phy", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
+			RV1106_SUBDDRCLKGATE_CON(0), 6, GFLAGS),
+	GATE(ACLK_DDRC, "aclk_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
+			RV1106_SUBDDRCLKGATE_CON(0), 1, GFLAGS),
+	GATE(CLK_CORE_DDRC, "clk_core_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
+			RV1106_SUBDDRCLKGATE_CON(0), 3, GFLAGS),
+
+	/* PD_VEPU */
+	COMPOSITE_NODIV(HCLK_VEPU_ROOT, "hclk_vepu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VEPUCLKSEL_CON(0), 0, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VEPU_COM_ROOT, "aclk_vepu_com_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VEPUCLKSEL_CON(0), 2, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VEPU_ROOT, "aclk_vepu_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VEPUCLKSEL_CON(0), 4, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 2, GFLAGS),
+	COMPOSITE_NODIV(PCLK_VEPU_ROOT, "pclk_vepu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VEPUCLKSEL_CON(0), 6, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 3, GFLAGS),
+	GATE(PCLK_SPI0, "pclk_spi0", "pclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(1), 2, GFLAGS),
+	COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
+			RV1106_VEPUCLKSEL_CON(0), 12, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(1), 3, GFLAGS),
+	GATE(CLK_UART_DETN_FLT, "clk_uart_detn_flt", "xin24m", 0,
+			RV1106_VEPUCLKGATE_CON(1), 8, GFLAGS),
+	GATE(HCLK_VEPU, "hclk_vepu", "hclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(0), 8, GFLAGS),
+	GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(0), 9, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", mux_400m_300m_pvtpll0_pvtpll1_p, 0,
+			RV1106_VEPUCLKSEL_CON(0), 8, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 10, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_VEPU_DVBM, "clk_core_vepu_dvbm", mux_200m_100m_50m_24m_p, 0,
+			RV1106_VEPUCLKSEL_CON(0), 10, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 13, GFLAGS),
+	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(0), 15, GFLAGS),
+	GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
+			RV1106_VEPUCLKGATE_CON(1), 0, GFLAGS),
+	GATE(HCLK_VEPU_PP, "hclk_vepu_pp", "hclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(0), 11, GFLAGS),
+	GATE(ACLK_VEPU_PP, "aclk_vepu_pp", "aclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(0), 12, GFLAGS),
+
+	/* PD_VI */
+	COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VICLKSEL_CON(0), 0, 2, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VI_ROOT, "aclk_vi_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VICLKSEL_CON(0), 2, 2, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VICLKSEL_CON(0), 4, 2, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 2, GFLAGS),
+	COMPOSITE_NODIV(PCLK_VI_RTC_ROOT, "pclk_vi_rtc_root", mux_50m_24m_p, 0,
+			RV1106_VICLKSEL_CON(0), 6, 1, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 3, GFLAGS),
+
+	GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(1), 3, GFLAGS),
+	GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(1), 5, GFLAGS),
+	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(1), 15, GFLAGS),
+	GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
+			RV1106_VICLKGATE_CON(2), 0, GFLAGS),
+	GATE(HCLK_ISP3P2, "hclk_isp3p2", "hclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(0), 7, GFLAGS),
+	GATE(ACLK_ISP3P2, "aclk_isp3p2", "aclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(0), 8, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_ISP3P2, "clk_core_isp3p2", mux_339m_200m_pvtpll0_pvtpll1_p, 0,
+			RV1106_VICLKSEL_CON(0), 7, 2, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 9, GFLAGS),
+	GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(1), 14, GFLAGS),
+	COMPOSITE(CCLK_SRC_SDMMC, "cclk_src_sdmmc", mux_400m_24m_p, 0,
+			RV1106_VICLKSEL_CON(1), 14, 1, MFLAGS, 8, 6, DFLAGS,
+			RV1106_VICLKGATE_CON(1), 11, GFLAGS),
+	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(1), 12, GFLAGS),
+	GATE(CLK_SDMMC_DETN_FLT, "clk_sdmmc_detn_flt", "xin24m", 0,
+			RV1106_VICLKGATE_CON(1), 13, GFLAGS),
+	GATE(PCLK_VI_RTC_TEST, "pclk_vi_rtc_test", "pclk_vi_rtc_root", 0,
+			RV1106_VICLKGATE_CON(2), 5, GFLAGS),
+	GATE(PCLK_VI_RTC_PHY, "pclk_vi_rtc_phy", "pclk_vi_rtc_root", 0,
+			RV1106_VICLKGATE_CON(2), 6, GFLAGS),
+	COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", mux_339m_200m_100m_24m_p, 0,
+			RV1106_VICLKSEL_CON(0), 9, 2, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 10, GFLAGS),
+	GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(0), 12, GFLAGS),
+	GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(0), 13, GFLAGS),
+
+	/* PD_VO */
+	COMPOSITE_NODIV(ACLK_MAC_ROOT, "aclk_mac_root", mux_300m_200m_100m_24m_p, 0,
+			RV1106_VOCLKSEL_CON(1), 12, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(1), 4, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VOCLKSEL_CON(0), 0, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VOCLKSEL_CON(0), 2, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VOCLKSEL_CON(0), 4, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(0), 2, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VOP_ROOT, "aclk_vop_root", mux_300m_200m_100m_24m_p, 0,
+			RV1106_VOCLKSEL_CON(1), 10, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(0), 11, GFLAGS),
+
+	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(3), 0, GFLAGS),
+	GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
+			RV1106_VOCLKGATE_CON(3), 1, GFLAGS),
+	GATE(ACLK_MAC, "aclk_mac", "aclk_mac_root", 0,
+			RV1106_VOCLKGATE_CON(1), 8, GFLAGS),
+	GATE(PCLK_MAC, "pclk_mac", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(1), 9, GFLAGS),
+	FACTOR(CLK_GMAC0_50M_O, "clk_gmac0_50m_o", "clk_50m_src", 0, 1, 1),
+	FACTOR(CLK_GMAC0_REF_50M, "clk_gmac0_ref_50m", "clk_gmac0_50m_o", 0, 1, 1),
+	DIV(CLK_GMAC0_TX_50M_O, "clk_gmac0_tx_50m_o", "clk_gmac0_50m_o", 0,
+			RV1106_VOCLKSEL_CON(2), 1, 6, DFLAGS),
+	GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
+			RV1106_VOCLKGATE_CON(2), 13, GFLAGS),
+	GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
+			RV1106_VOCLKGATE_CON(2), 11, GFLAGS),
+	GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(2), 3, GFLAGS),
+	GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
+			RV1106_VOCLKGATE_CON(2), 5, GFLAGS),
+	COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
+			RV1106_VOCLKSEL_CON(3), 10, 3, DFLAGS,
+			RV1106_VOCLKGATE_CON(2), 6, GFLAGS),
+	GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(2), 7, GFLAGS),
+	GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", 0,
+			RV1106_VOCLKGATE_CON(2), 9, GFLAGS),
+	COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", 0,
+			RV1106_VOCLKSEL_CON(3), 13, 3, DFLAGS,
+			RV1106_VOCLKGATE_CON(2), 10, GFLAGS),
+	GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(2), 14, GFLAGS),
+	GATE(CLK_PMC_OTP, "clk_pmc_otp", "clk_sbpi_otpc_s", 0,
+			RV1106_VOCLKGATE_CON(2), 15, GFLAGS),
+	GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(0), 7, GFLAGS),
+	GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(0), 8, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_400m_200m_100m_24m_p, 0,
+			RV1106_VOCLKSEL_CON(1), 8, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(0), 9, GFLAGS),
+	COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", mux_400m_24m_p, 0,
+			RV1106_VOCLKSEL_CON(2), 13, 1, MFLAGS, 7, 6, DFLAGS,
+			RV1106_VOCLKGATE_CON(1), 14, GFLAGS),
+	GATE(HCLK_SDIO, "hclk_sdio", "hclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(1), 15, GFLAGS),
+	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(2), 0, GFLAGS),
+	COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
+			RV1106_VOCLKSEL_CON(3), 0, 5, DFLAGS,
+			RV1106_VOCLKGATE_CON(2), 1, GFLAGS),
+	COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
+			RV1106_VOCLKSEL_CON(3), 5, 5, DFLAGS,
+			RV1106_VOCLKGATE_CON(2), 2, GFLAGS),
+	GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(0), 13, GFLAGS),
+	GATE(DCLK_VOP, "dclk_vop", "dclk_vop_src", 0,
+			RV1106_VOCLKGATE_CON(0), 14, GFLAGS),
+	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
+			RV1106_VOCLKGATE_CON(0), 15, GFLAGS),
+
+	/* IO CLK */
+	GATE(RX0PCLK_VICAP, "rx0pclk_vicap", "rx0pclk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(1), 0, GFLAGS),
+	GATE(RX1PCLK_VICAP, "rx1pclk_vicap", "rx1pclk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(1), 1, GFLAGS),
+	GATE(ISP0CLK_VICAP, "isp0clk_vicap", "isp0clk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(1), 2, GFLAGS),
+	GATE(I0CLK_VICAP, "i0clk_vicap", "i0clk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(0), 14, GFLAGS),
+	GATE(I1CLK_VICAP, "i1clk_vicap", "i1clk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(0), 15, GFLAGS),
+	GATE(PCLK_VICAP, "pclk_vicap", "pclk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(0), 11, GFLAGS),
+	GATE(CLK_RXBYTECLKHS_0, "clk_rxbyteclkhs_0", "clk_rxbyteclkhs_0_io", 0,
+			RV1106_VICLKGATE_CON(1), 4, GFLAGS),
+	GATE(CLK_RXBYTECLKHS_1, "clk_rxbyteclkhs_1", "clk_rxbyteclkhs_1_io", 0,
+			RV1106_VICLKGATE_CON(1), 6, GFLAGS),
+
+	GATE(PCLK_VICAP_VEPU, "pclk_vicap_vepu", "pclk_vicap_vepu_io", 0,
+			RV1106_VEPUCLKGATE_CON(0), 14, GFLAGS),
+	GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0,
+			RV1106_VEPUCLKGATE_CON(1), 4, GFLAGS),
+
+	GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
+			RV1106_PERICLKGATE_CON(4), 9, GFLAGS),
+};
+
+static struct rockchip_clk_branch rv1106_grf_clk_branches[] __initdata = {
+	MMC_GRF(SCLK_EMMC_DRV, "emmc_drv", "cclk_src_emmc",
+		RV1106_EMMC_CON0, 1, grf_type_sys),
+	MMC_GRF(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_src_emmc",
+		RV1106_EMMC_CON1, 1, grf_type_sys),
+	MMC_GRF(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc",
+		RV1106_SDMMC_CON0, 1, grf_type_sys),
+	MMC_GRF(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc",
+		RV1106_SDMMC_CON1, 1, grf_type_sys),
+	MMC_GRF(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio",
+		RV1106_SDIO_CON0, 1, grf_type_sys),
+	MMC_GRF(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio",
+		RV1106_SDIO_CON1, 1, grf_type_sys),
+};
+
+static void __init rv1106_pvtpll_init(struct rockchip_clk_provider *ctx)
+{
+	/* set pvtpll ref clk mux */
+	writel_relaxed(CPU_PVTPLL_PATH_CORE, ctx->reg_base + CPU_CLK_PATH_BASE);
+
+	if (!IS_ERR(ctx->grf)) {
+		regmap_write(ctx->grf, CPU_PVTPLL_CON0_H,
+			     HIWORD_UPDATE(0x7, PVTPLL_LENGTH_SEL_MASK,
+					   PVTPLL_LENGTH_SEL_SHIFT));
+		regmap_write(ctx->grf, CPU_PVTPLL_CON0_L,
+			     HIWORD_UPDATE(0x1, PVTPLL_RING_SEL_MASK,
+					   PVTPLL_RING_SEL_SHIFT));
+		regmap_write(ctx->grf, CPU_PVTPLL_CON0_L,
+			     HIWORD_UPDATE(0x3, PVTPLL_EN_MASK,
+					   PVTPLL_EN_SHIFT));
+	}
+
+	writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL0_CON0_H);
+	writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL0_CON1_L);
+	writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL0_CON2_H);
+	writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL0_CON0_L);
+
+	writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL1_CON0_H);
+	writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL1_CON1_L);
+	writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL1_CON2_H);
+	writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL1_CON0_L);
+}
+
+static void __init rv1106_clk_init(struct device_node *np)
+{
+	struct rockchip_clk_provider *ctx;
+	unsigned long clk_nr;
+	void __iomem *reg_base;
+	int ret;
+
+	clk_nr = rockchip_clk_find_max_clk_id(rv1106_clk_branches,
+					      ARRAY_SIZE(rv1106_clk_branches)) + 1;
+	clk_nr = max(clk_nr,
+		     rockchip_clk_find_max_clk_id(rv1106_grf_clk_branches,
+					ARRAY_SIZE(rv1106_grf_clk_branches)) + 1);
+	reg_base = of_iomap(np, 0);
+	if (!reg_base) {
+		pr_err("%s: could not map cru region\n", __func__);
+		return;
+	}
+
+	ctx = rockchip_clk_init(np, reg_base, clk_nr);
+	if (IS_ERR(ctx)) {
+		pr_err("%s: rockchip clk init failed\n", __func__);
+		iounmap(reg_base);
+		return;
+	}
+
+	rv1106_pvtpll_init(ctx);
+
+	rockchip_clk_register_plls(ctx, rv1106_pll_clks,
+				   ARRAY_SIZE(rv1106_pll_clks),
+				   RV1106_GRF_SOC_STATUS0);
+
+	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
+				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+				     &rv1106_cpuclk_data, rv1106_cpuclk_rates,
+				     ARRAY_SIZE(rv1106_cpuclk_rates));
+
+	rockchip_clk_register_branches(ctx, rv1106_clk_branches,
+				       ARRAY_SIZE(rv1106_clk_branches));
+
+	/*
+	 * The MMC drive and sample phase clocks have their control
+	 * registers in the GRF region, so they can only be provided when
+	 * the rockchip,grf property points at a valid syscon.
+	 */
+	if (!IS_ERR(ctx->grf)) {
+		ret = rockchip_clk_add_grf(ctx, ctx->grf, grf_type_sys);
+		if (ret)
+			pr_err("%s: failed to add grf: %d\n", __func__, ret);
+		else
+			rockchip_clk_register_branches(ctx,
+					rv1106_grf_clk_branches,
+					ARRAY_SIZE(rv1106_grf_clk_branches));
+	}
+
+	rockchip_register_restart_notifier(ctx, RV1106_GLB_SRST_FST, NULL);
+
+	rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rv1106_cru, "rockchip,rv1106-cru", rv1106_clk_init);
-- 
2.43.0

[PATCH v2 3/6] dt-bindings: soc: rockchip: grf: Add RV1106 compatibles

[Simon Glass]

Add the compatibles for the general register files of the Rockchip
RV1106: the main GRF, and the per-bank GPIO IOC blocks used by the pin
controller.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Drop the grf-cru clock-controller child and use the syscon-only
  group for the main GRF, since the CRU now provides the MMC phase
  clocks
- Use a single gpio-ioc compatible for the per-bank IOC blocks in
  place of the ioc and pmuioc regions

 Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 2cc43742b8e3..fd9235ac1334 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -64,6 +64,8 @@ properties:
               - rockchip,rk3588-vo1-grf
               - rockchip,rk3588-vop-grf
               - rockchip,rv1103b-ioc
+              - rockchip,rv1106-gpio-ioc
+              - rockchip,rv1106-grf
               - rockchip,rv1108-usbgrf
           - const: syscon
       - items:
-- 
2.43.0

[PATCH v2 4/6] ARM: dts: rockchip: Add support for RV1106 and RV1103

[Simon Glass]

Add the devicetree files for the Rockchip RV1106, a Cortex-A7 SoC
aimed at IP cameras, and its RV1103 package variant, which has fewer
pins and no GPIO2 bank. The pinctrl data comes from the vendor kernel in
the Luckfox Pico  SDK [1] at commit 824b817f8 (a Linux 5.10.160 kernel
tree).

[1] https://github.com/LuckfoxTECH/luckfox-pico

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Take the MMC drive and sample phase clocks from the CRU and drop the
  grf-cru node
- Give each GPIO bank a syscon for its own IOC block, referenced by a
  rockchip,grf phandle in the bank node
- Add gpio aliases, which the pin controller and gpio drivers use to
  identify the bank; the rv1103 removes the gpio2 alias

 arch/arm/boot/dts/rockchip/rv1103.dtsi        |   16 +
 .../arm/boot/dts/rockchip/rv1106-pinctrl.dtsi | 1398 +++++++++++++++++
 arch/arm/boot/dts/rockchip/rv1106.dtsi        |  321 ++++
 3 files changed, 1735 insertions(+)
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103.dtsi
 create mode 100644 arch/arm/boot/dts/rockchip/rv1106-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/rockchip/rv1106.dtsi

diff --git a/arch/arm/boot/dts/rockchip/rv1103.dtsi b/arch/arm/boot/dts/rockchip/rv1103.dtsi
new file mode 100644
index 000000000000..025fde5bf09c
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1103.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rv1106.dtsi"
+
+/ {
+	compatible = "rockchip,rv1103";
+
+	aliases {
+		/delete-property/ gpio2;
+	};
+};
+
+/delete-node/ &gpio2;
diff --git a/arch/arm/boot/dts/rockchip/rv1106-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1106-pinctrl.dtsi
new file mode 100644
index 000000000000..289634f5adb3
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1106-pinctrl.dtsi
@@ -0,0 +1,1398 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <arm64/rockchip/rockchip-pinconf.dtsi>
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+	adc {
+		/omit-if-no-ref/
+		adc_pins: adc-pins {
+			rockchip,pins =
+				/* adc_in0 */
+				<4 RK_PC0 1 &pcfg_pull_none>,
+				/* adc_in1 */
+				<4 RK_PC1 1 &pcfg_pull_none>;
+		};
+	};
+
+	avs {
+		/omit-if-no-ref/
+		avs_pins: avs-pins {
+			rockchip,pins =
+				/* avs_arm */
+				<1 RK_PA2 2 &pcfg_pull_none>;
+		};
+	};
+
+	clk {
+		/omit-if-no-ref/
+		clk_32k: clk-32k {
+			rockchip,pins =
+				/* clk_32k */
+				<0 RK_PA0 2 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		clk_refout: clk-refout {
+			rockchip,pins =
+				/* clk_refout */
+				<0 RK_PA0 3 &pcfg_pull_none>;
+		};
+	};
+
+	dsmaudio {
+		/omit-if-no-ref/
+		dsmaudio_pins: dsmaudio-pins {
+			rockchip,pins =
+				/* dsmaudio_n */
+				<1 RK_PD3 7 &pcfg_pull_none>,
+				/* dsmaudio_p */
+				<1 RK_PD2 7 &pcfg_pull_none>;
+		};
+	};
+
+	emmc {
+		/omit-if-no-ref/
+		emmc_bus8: emmc-bus8 {
+			rockchip,pins =
+				/* emmc_d0 */
+				<4 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d1 */
+				<4 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d2 */
+				<4 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d3 */
+				<4 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d4 */
+				<4 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d5 */
+				<4 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d6 */
+				<4 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d7 */
+				<4 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		emmc_clk: emmc-clk {
+			rockchip,pins =
+				/* emmc_clk */
+				<4 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		emmc_cmd: emmc-cmd {
+			rockchip,pins =
+				/* emmc_cmd */
+				<4 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+		};
+	};
+
+	flash {
+		/omit-if-no-ref/
+		flash_pins: flash-pins {
+			rockchip,pins =
+				/* flash_trig_out */
+				<2 RK_PA6 6 &pcfg_pull_none>;
+		};
+	};
+
+	fspi {
+		/omit-if-no-ref/
+		fspi_pins: fspi-pins {
+			rockchip,pins =
+				/* fspi_clk */
+				<4 RK_PB1 2 &pcfg_pull_up_drv_level_2>,
+				/* fspi_d0 */
+				<4 RK_PA4 2 &pcfg_pull_none>,
+				/* fspi_d1 */
+				<4 RK_PA3 2 &pcfg_pull_none>,
+				/* fspi_d2 */
+				<4 RK_PA2 2 &pcfg_pull_none>,
+				/* fspi_d3 */
+				<4 RK_PA6 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		fspi_cs0: fspi-cs0 {
+			rockchip,pins =
+				/* fspi_cs0n */
+				<4 RK_PB0 2 &pcfg_pull_up>;
+		};
+	};
+
+	hpmcu {
+		/omit-if-no-ref/
+		hpmcum0_pins: hpmcum0-pins {
+			rockchip,pins =
+				/* hpmcu_jtag_tck_m0 */
+				<1 RK_PB2 3 &pcfg_pull_none>,
+				/* hpmcu_jtag_tms_m0 */
+				<1 RK_PB3 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		hpmcum1_pins: hpmcum1-pins {
+			rockchip,pins =
+				/* hpmcu_jtag_tck_m1 */
+				<3 RK_PA7 4 &pcfg_pull_none>,
+				/* hpmcu_jtag_tms_m1 */
+				<3 RK_PA6 4 &pcfg_pull_none>;
+		};
+	};
+
+	i2c0 {
+		/omit-if-no-ref/
+		i2c0m0_xfer: i2c0m0-xfer {
+			rockchip,pins =
+				/* i2c0_scl_m0 */
+				<1 RK_PA3 2 &pcfg_pull_none_smt>,
+				/* i2c0_sda_m0 */
+				<1 RK_PA4 2 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c0m1_xfer: i2c0m1-xfer {
+			rockchip,pins =
+				/* i2c0_scl_m1 */
+				<4 RK_PA1 4 &pcfg_pull_none_smt>,
+				/* i2c0_sda_m1 */
+				<4 RK_PA0 4 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c0m2_xfer: i2c0m2-xfer {
+			rockchip,pins =
+				/* i2c0_scl_m2 */
+				<3 RK_PA4 3 &pcfg_pull_none_smt>,
+				/* i2c0_sda_m2 */
+				<3 RK_PA5 3 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c1 {
+		/omit-if-no-ref/
+		i2c1m0_xfer: i2c1m0-xfer {
+			rockchip,pins =
+				/* i2c1_scl_m0 */
+				<0 RK_PA5 1 &pcfg_pull_none_smt>,
+				/* i2c1_sda_m0 */
+				<0 RK_PA6 1 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c1m1_xfer: i2c1m1-xfer {
+			rockchip,pins =
+				/* i2c1_scl_m1 */
+				<2 RK_PB0 2 &pcfg_pull_none_smt>,
+				/* i2c1_sda_m1 */
+				<2 RK_PB1 2 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c2 {
+		/omit-if-no-ref/
+		i2c2m0_xfer: i2c2m0-xfer {
+			rockchip,pins =
+				/* i2c2_scl_m0 */
+				<1 RK_PA0 2 &pcfg_pull_none_smt>,
+				/* i2c2_sda_m0 */
+				<1 RK_PA1 2 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c2m1_xfer: i2c2m1-xfer {
+			rockchip,pins =
+				/* i2c2_scl_m1 */
+				<4 RK_PA7 4 &pcfg_pull_none_smt>,
+				/* i2c2_sda_m1 */
+				<4 RK_PA5 4 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c3 {
+		/omit-if-no-ref/
+		i2c3m0_xfer: i2c3m0-xfer {
+			rockchip,pins =
+				/* i2c3_scl_m0 */
+				<2 RK_PA6 5 &pcfg_pull_none_smt>,
+				/* i2c3_sda_m0 */
+				<2 RK_PA7 5 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c3m1_xfer: i2c3m1-xfer {
+			rockchip,pins =
+				/* i2c3_scl_m1 */
+				<1 RK_PD3 3 &pcfg_pull_none_smt>,
+				/* i2c3_sda_m1 */
+				<1 RK_PD2 3 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c3m2_xfer: i2c3m2-xfer {
+			rockchip,pins =
+				/* i2c3_scl_m2 */
+				<3 RK_PD1 3 &pcfg_pull_none_smt>,
+				/* i2c3_sda_m2 */
+				<3 RK_PD2 3 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c4 {
+		/omit-if-no-ref/
+		i2c4m0_xfer: i2c4m0-xfer {
+			rockchip,pins =
+				/* i2c4_scl_m0 */
+				<2 RK_PA1 5 &pcfg_pull_none_smt>,
+				/* i2c4_sda_m0 */
+				<2 RK_PA0 5 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c4m1_xfer: i2c4m1-xfer {
+			rockchip,pins =
+				/* i2c4_scl_m1 */
+				<1 RK_PC2 4 &pcfg_pull_none_smt>,
+				/* i2c4_sda_m1 */
+				<1 RK_PC3 4 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c4m2_xfer: i2c4m2-xfer {
+			rockchip,pins =
+				/* i2c4_scl_m2 */
+				<3 RK_PC7 3 &pcfg_pull_none_smt>,
+				/* i2c4_sda_m2 */
+				<3 RK_PD0 3 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2s0 {
+		/omit-if-no-ref/
+		i2s0_pins: i2s0-pins {
+			rockchip,pins =
+				/* i2s0_lrck */
+				<2 RK_PA1 2 &pcfg_pull_none>,
+				/* i2s0_mclk */
+				<2 RK_PA2 2 &pcfg_pull_none>,
+				/* i2s0_sclk */
+				<2 RK_PA0 2 &pcfg_pull_none>,
+				/* i2s0_sdi0 */
+				<2 RK_PA5 2 &pcfg_pull_none>,
+				/* i2s0_sdo0 */
+				<2 RK_PA4 2 &pcfg_pull_none>,
+				/* i2s0_sdo1_sdi3 */
+				<2 RK_PA7 2 &pcfg_pull_none>,
+				/* i2s0_sdo2_sdi2 */
+				<2 RK_PA6 2 &pcfg_pull_none>,
+				/* i2s0_sdo3_sdi1 */
+				<2 RK_PA3 2 &pcfg_pull_none>;
+		};
+	};
+
+	lcd {
+		/omit-if-no-ref/
+		lcd_pins: lcd-pins {
+			rockchip,pins =
+				/* lcd_clk */
+				<1 RK_PD3 1 &pcfg_pull_none_drv_level_4>,
+				/* lcd_d0 */
+				<1 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d1 */
+				<1 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d2 */
+				<1 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d3 */
+				<1 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d4 */
+				<1 RK_PC3 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d5 */
+				<1 RK_PC2 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d6 */
+				<1 RK_PC1 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d7 */
+				<1 RK_PC0 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d8 */
+				<2 RK_PA0 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d9 */
+				<2 RK_PA1 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d10 */
+				<2 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d11 */
+				<2 RK_PA3 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d12 */
+				<2 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d13 */
+				<2 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d14 */
+				<2 RK_PA6 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d15 */
+				<2 RK_PA7 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d16 */
+				<2 RK_PB0 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d17 */
+				<2 RK_PB1 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_den */
+				<1 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_hsync */
+				<1 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_vsync */
+				<1 RK_PD2 1 &pcfg_pull_none_drv_level_3>;
+		};
+	};
+
+	lpmcu {
+		/omit-if-no-ref/
+		lpmcum0_pins: lpmcum0-pins {
+			rockchip,pins =
+				/* lpmcu_jtag_tck_m0 */
+				<1 RK_PB2 4 &pcfg_pull_none>,
+				/* lpmcu_jtag_tms_m0 */
+				<1 RK_PB3 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		lpmcum1_pins: lpmcum1-pins {
+			rockchip,pins =
+				/* lpmcu_jtag_tck_m1 */
+				<3 RK_PA4 4 &pcfg_pull_none>,
+				/* lpmcu_jtag_tms_m1 */
+				<3 RK_PA5 4 &pcfg_pull_none>;
+		};
+	};
+
+	mipi {
+		/omit-if-no-ref/
+		mipi_pins: mipi-pins {
+			rockchip,pins =
+				/* mipi_lvds_ck0n */
+				<3 RK_PC0 2 &pcfg_pull_none>,
+				/* mipi_lvds_ck0p */
+				<3 RK_PC1 2 &pcfg_pull_none>,
+				/* mipi_lvds_ck1n */
+				<3 RK_PB2 2 &pcfg_pull_none>,
+				/* mipi_lvds_ck1p */
+				<3 RK_PB3 2 &pcfg_pull_none>,
+				/* mipi_lvds_d0n */
+				<3 RK_PC2 2 &pcfg_pull_none>,
+				/* mipi_lvds_d0p */
+				<3 RK_PC3 2 &pcfg_pull_none>,
+				/* mipi_lvds_d1n */
+				<3 RK_PB6 2 &pcfg_pull_none>,
+				/* mipi_lvds_d1p */
+				<3 RK_PB7 2 &pcfg_pull_none>,
+				/* mipi_lvds_d2n */
+				<3 RK_PB4 2 &pcfg_pull_none>,
+				/* mipi_lvds_d2p */
+				<3 RK_PB5 2 &pcfg_pull_none>,
+				/* mipi_lvds_d3n */
+				<3 RK_PB0 2 &pcfg_pull_none>,
+				/* mipi_lvds_d3p */
+				<3 RK_PB1 2 &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		/omit-if-no-ref/
+		pmicm0_pins: pmicm0-pins {
+			rockchip,pins =
+				/* pmic_sleep_m0 */
+				<0 RK_PA4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pmicm1_pins: pmicm1-pins {
+			rockchip,pins =
+				/* pmic_sleep_m1 */
+				<0 RK_PA3 1 &pcfg_pull_none>;
+		};
+	};
+
+	pmu {
+		/omit-if-no-ref/
+		pmu_pins: pmu-pins {
+			rockchip,pins =
+				/* pmu_debug */
+				<1 RK_PA1 3 &pcfg_pull_none>;
+		};
+	};
+
+	prelight {
+		/omit-if-no-ref/
+		prelight_pins: prelight-pins {
+			rockchip,pins =
+				/* prelight_trig_out */
+				<2 RK_PA7 6 &pcfg_pull_none>;
+		};
+	};
+
+	pwm0 {
+		/omit-if-no-ref/
+		pwm0m0_pins: pwm0m0-pins {
+			rockchip,pins =
+				/* pwm0_m0 */
+				<1 RK_PA2 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm0m1_pins: pwm0m1-pins {
+			rockchip,pins =
+				/* pwm0_m1 */
+				<1 RK_PD2 6 &pcfg_pull_none>;
+		};
+	};
+
+	pwm1 {
+		/omit-if-no-ref/
+		pwm1m0_pins: pwm1m0-pins {
+			rockchip,pins =
+				/* pwm1_m0 */
+				<0 RK_PA4 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm1m1_pins: pwm1m1-pins {
+			rockchip,pins =
+				/* pwm1_m1 */
+				<4 RK_PC1 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm1m2_pins: pwm1m2-pins {
+			rockchip,pins =
+				/* pwm1_m2 */
+				<3 RK_PD3 2 &pcfg_pull_none>;
+		};
+	};
+
+	pwm2 {
+		/omit-if-no-ref/
+		pwm2m0_pins: pwm2m0-pins {
+			rockchip,pins =
+				/* pwm2_m0 */
+				<0 RK_PA1 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm2m1_pins: pwm2m1-pins {
+			rockchip,pins =
+				/* pwm2_m1 */
+				<2 RK_PA6 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm2m2_pins: pwm2m2-pins {
+			rockchip,pins =
+				/* pwm2_m2 */
+				<1 RK_PC0 3 &pcfg_pull_none>;
+		};
+	};
+
+	pwm3 {
+		/omit-if-no-ref/
+		pwm3m0_pins: pwm3m0-pins {
+			rockchip,pins =
+				/* pwm3_ir_m0 */
+				<0 RK_PA2 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm3m1_pins: pwm3m1-pins {
+			rockchip,pins =
+				/* pwm3_ir_m1 */
+				<1 RK_PB0 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm3m2_pins: pwm3m2-pins {
+			rockchip,pins =
+				/* pwm3_ir_m2 */
+				<1 RK_PD0 3 &pcfg_pull_none>;
+		};
+	};
+
+	pwm4 {
+		/omit-if-no-ref/
+		pwm4m0_pins: pwm4m0-pins {
+			rockchip,pins =
+				/* pwm4_m0 */
+				<1 RK_PA1 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm4m1_pins: pwm4m1-pins {
+			rockchip,pins =
+				/* pwm4_m1 */
+				<2 RK_PA7 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm4m2_pins: pwm4m2-pins {
+			rockchip,pins =
+				/* pwm4_m2 */
+				<1 RK_PC1 3 &pcfg_pull_none>;
+		};
+	};
+
+	pwm5 {
+		/omit-if-no-ref/
+		pwm5m0_pins: pwm5m0-pins {
+			rockchip,pins =
+				/* pwm5_m0 */
+				<0 RK_PA5 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm5m1_pins: pwm5m1-pins {
+			rockchip,pins =
+				/* pwm5_m1 */
+				<2 RK_PB0 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm5m2_pins: pwm5m2-pins {
+			rockchip,pins =
+				/* pwm5_m2 */
+				<1 RK_PC2 3 &pcfg_pull_none>;
+		};
+	};
+
+	pwm6 {
+		/omit-if-no-ref/
+		pwm6m0_pins: pwm6m0-pins {
+			rockchip,pins =
+				/* pwm6_m0 */
+				<0 RK_PA6 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm6m1_pins: pwm6m1-pins {
+			rockchip,pins =
+				/* pwm6_m1 */
+				<2 RK_PB1 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm6m2_pins: pwm6m2-pins {
+			rockchip,pins =
+				/* pwm6_m2 */
+				<1 RK_PC3 3 &pcfg_pull_none>;
+		};
+	};
+
+	pwm7 {
+		/omit-if-no-ref/
+		pwm7m0_pins: pwm7m0-pins {
+			rockchip,pins =
+				/* pwm7_ir_m0 */
+				<1 RK_PA0 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm7m1_pins: pwm7m1-pins {
+			rockchip,pins =
+				/* pwm7_ir_m1 */
+				<1 RK_PB1 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm7m2_pins: pwm7m2-pins {
+			rockchip,pins =
+				/* pwm7_ir_m2 */
+				<3 RK_PC6 2 &pcfg_pull_none>;
+		};
+	};
+
+	pwm8 {
+		/omit-if-no-ref/
+		pwm8m0_pins: pwm8m0-pins {
+			rockchip,pins =
+				/* pwm8_m0 */
+				<3 RK_PA3 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm8m1_pins: pwm8m1-pins {
+			rockchip,pins =
+				/* pwm8_m1 */
+				<1 RK_PC4 3 &pcfg_pull_none>;
+		};
+	};
+
+	pwm9 {
+		/omit-if-no-ref/
+		pwm9m0_pins: pwm9m0-pins {
+			rockchip,pins =
+				/* pwm9_m0 */
+				<3 RK_PA2 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm9m1_pins: pwm9m1-pins {
+			rockchip,pins =
+				/* pwm9_m1 */
+				<1 RK_PC5 3 &pcfg_pull_none>;
+		};
+	};
+
+	pwm10 {
+		/omit-if-no-ref/
+		pwm10m0_pins: pwm10m0-pins {
+			rockchip,pins =
+				/* pwm10_m0 */
+				<3 RK_PA4 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm10m1_pins: pwm10m1-pins {
+			rockchip,pins =
+				/* pwm10_m1 */
+				<1 RK_PC6 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm10m2_pins: pwm10m2-pins {
+			rockchip,pins =
+				/* pwm10_m2 */
+				<1 RK_PD1 3 &pcfg_pull_none>;
+		};
+	};
+
+	pwm11 {
+		/omit-if-no-ref/
+		pwm11m0_pins: pwm11m0-pins {
+			rockchip,pins =
+				/* pwm11_ir_m0 */
+				<3 RK_PA5 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm11m1_pins: pwm11m1-pins {
+			rockchip,pins =
+				/* pwm11_ir_m1 */
+				<1 RK_PC7 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm11m2_pins: pwm11m2-pins {
+			rockchip,pins =
+				/* pwm11_ir_m2 */
+				<1 RK_PD3 5 &pcfg_pull_none>;
+		};
+	};
+
+	rtc {
+		/omit-if-no-ref/
+		rtc_pins: rtc-pins {
+			rockchip,pins =
+				/* rtc_clko */
+				<0 RK_PA0 4 &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc0 {
+		/omit-if-no-ref/
+		sdmmc0_bus4: sdmmc0-bus4 {
+			rockchip,pins =
+				/* sdmmc0_d0 */
+				<3 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc0_d1 */
+				<3 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc0_d2 */
+				<3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc0_d3 */
+				<3 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc0_clk: sdmmc0-clk {
+			rockchip,pins =
+				/* sdmmc0_clk */
+				<3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc0_cmd: sdmmc0-cmd {
+			rockchip,pins =
+				/* sdmmc0_cmd */
+				<3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc0_det: sdmmc0-det {
+			rockchip,pins =
+				/* sdmmc0_det */
+				<3 RK_PA1 1 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc0_idle_pins: sdmmc0-idle-pins {
+			rockchip,pins =
+				<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>,
+				<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>,
+				<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>,
+				<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>,
+				<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>,
+				<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	sdmmc1 {
+		/omit-if-no-ref/
+		sdmmc1m0_bus1: sdmmc1m0-bus1 {
+			rockchip,pins =
+				/* sdmmc1_d0_m0 */
+				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1m0_bus4: sdmmc1m0-bus4 {
+			rockchip,pins =
+				/* sdmmc1_d0_m0 */
+				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d1_m0 */
+				<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d2_m0 */
+				<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d3_m0 */
+				<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1m0_clk: sdmmc1m0-clk {
+			rockchip,pins =
+				/* sdmmc1_clk_m0 */
+				<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1m0_cmd: sdmmc1m0-cmd {
+			rockchip,pins =
+				/* sdmmc1_cmd_m0 */
+				<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1m0_idle_pins: sdmmc1m0-idle-pins {
+			rockchip,pins =
+				<2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>,
+				<2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>,
+				<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>,
+				<2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>,
+				<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>,
+				<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1m1_bus4: sdmmc1m1-bus4 {
+			rockchip,pins =
+				/* sdmmc1_d0_m1 */
+				<1 RK_PC1 5 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d1_m1 */
+				<1 RK_PC0 5 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d2_m1 */
+				<1 RK_PC5 5 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d3_m1 */
+				<1 RK_PC4 5 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1m1_clk: sdmmc1m1-clk {
+			rockchip,pins =
+				/* sdmmc1_clk_m1 */
+				<1 RK_PC2 5 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1m1_cmd: sdmmc1m1-cmd {
+			rockchip,pins =
+				/* sdmmc1_cmd_m1 */
+				<1 RK_PC3 5 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1m1_idle_pins: sdmmc1m1-idle-pins {
+			rockchip,pins =
+				<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>,
+				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
+				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>,
+				<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>,
+				<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>,
+				<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	spi0 {
+		/omit-if-no-ref/
+		spi0m0_pins: spi0m0-pins {
+			rockchip,pins =
+				/* spi0_clk_m0 */
+				<1 RK_PC1 4 &pcfg_pull_none>,
+				/* spi0_miso_m0 */
+				<1 RK_PC3 6 &pcfg_pull_none>,
+				/* spi0_mosi_m0 */
+				<1 RK_PC2 6 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi0m0_cs0: spi0m0-cs0 {
+			rockchip,pins =
+				/* spi0_cs0n_m0 */
+				<1 RK_PC0 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi0m0_cs1: spi0m0-cs1 {
+			rockchip,pins =
+				/* spi0_cs1n_m0 */
+				<1 RK_PD2 5 &pcfg_pull_none>;
+		};
+	};
+
+	spi1 {
+		/omit-if-no-ref/
+		spi1m0_pins: spi1m0-pins {
+			rockchip,pins =
+				/* spi1_clk_m0 */
+				<4 RK_PA7 2 &pcfg_pull_none>,
+				/* spi1_miso_m0 */
+				<4 RK_PA0 2 &pcfg_pull_none>,
+				/* spi1_mosi_m0 */
+				<4 RK_PA1 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi1m0_cs0: spi1m0-cs0 {
+			rockchip,pins =
+				/* spi1_cs0n_m0 */
+				<4 RK_PA5 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi1m0_cs1: spi1m0-cs1 {
+			rockchip,pins =
+				/* spi1_cs1n_m0 */
+				<1 RK_PB1 3 &pcfg_pull_none>;
+		};
+	};
+
+	uart0 {
+		/omit-if-no-ref/
+		uart0m0_xfer: uart0m0-xfer {
+			rockchip,pins =
+				/* uart0_rx_m0 */
+				<0 RK_PA0 1 &pcfg_pull_up>,
+				/* uart0_tx_m0 */
+				<0 RK_PA1 1 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart0m1_xfer: uart0m1-xfer {
+			rockchip,pins =
+				/* uart0_rx_m1 */
+				<2 RK_PB0 1 &pcfg_pull_up>,
+				/* uart0_tx_m1 */
+				<2 RK_PB1 1 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart0m1_ctsn: uart0m1-ctsn {
+			rockchip,pins =
+				/* uart0m1_ctsn */
+				<2 RK_PA7 1 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		uart0m1_rtsn: uart0m1-rtsn {
+			rockchip,pins =
+				/* uart0m1_rtsn */
+				<2 RK_PA6 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart0m2_xfer: uart0m2-xfer {
+			rockchip,pins =
+				/* uart0_rx_m2 */
+				<4 RK_PA0 3 &pcfg_pull_up>,
+				/* uart0_tx_m2 */
+				<4 RK_PA1 3 &pcfg_pull_up>;
+		};
+	};
+
+	uart1 {
+		/omit-if-no-ref/
+		uart1m0_xfer: uart1m0-xfer {
+			rockchip,pins =
+				/* uart1_rx_m0 */
+				<1 RK_PA4 1 &pcfg_pull_up>,
+				/* uart1_tx_m0 */
+				<1 RK_PA3 1 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart1m0_ctsn: uart1m0-ctsn {
+			rockchip,pins =
+				/* uart1m0_ctsn */
+				<0 RK_PA6 2 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		uart1m0_rtsn: uart1m0-rtsn {
+			rockchip,pins =
+				/* uart1m0_rtsn */
+				<0 RK_PA5 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart1m1_xfer: uart1m1-xfer {
+			rockchip,pins =
+				/* uart1_rx_m1 */
+				<2 RK_PA5 4 &pcfg_pull_up>,
+				/* uart1_tx_m1 */
+				<2 RK_PA4 4 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart1m1_ctsn: uart1m1-ctsn {
+			rockchip,pins =
+				/* uart1m1_ctsn */
+				<2 RK_PA0 4 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		uart1m1_rtsn: uart1m1-rtsn {
+			rockchip,pins =
+				/* uart1m1_rtsn */
+				<2 RK_PA1 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart1m2_xfer: uart1m2-xfer {
+			rockchip,pins =
+				/* uart1_rx_m2 */
+				<4 RK_PA7 3 &pcfg_pull_up>,
+				/* uart1_tx_m2 */
+				<4 RK_PA5 3 &pcfg_pull_up>;
+		};
+	};
+
+	uart2 {
+		/omit-if-no-ref/
+		uart2m0_xfer: uart2m0-xfer {
+			rockchip,pins =
+				/* uart2_rx_m0 */
+				<3 RK_PA3 2 &pcfg_pull_up>,
+				/* uart2_tx_m0 */
+				<3 RK_PA2 2 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart2m1_xfer: uart2m1-xfer {
+			rockchip,pins =
+				/* uart2_rx_m1 */
+				<1 RK_PB3 2 &pcfg_pull_up>,
+				/* uart2_tx_m1 */
+				<1 RK_PB2 2 &pcfg_pull_up>;
+		};
+	};
+
+	uart3 {
+		/omit-if-no-ref/
+		uart3m0_xfer: uart3m0-xfer {
+			rockchip,pins =
+				/* uart3_rx_m0 */
+				<1 RK_PA1 1 &pcfg_pull_up>,
+				/* uart3_tx_m0 */
+				<1 RK_PA0 1 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart3m1_xfer: uart3m1-xfer {
+			rockchip,pins =
+				/* uart3_rx_m1 */
+				<1 RK_PD1 5 &pcfg_pull_up>,
+				/* uart3_tx_m1 */
+				<1 RK_PD0 5 &pcfg_pull_up>;
+		};
+	};
+
+	uart4 {
+		/omit-if-no-ref/
+		uart4m0_xfer: uart4m0-xfer {
+			rockchip,pins =
+				/* uart4_rx_m0 */
+				<1 RK_PB0 1 &pcfg_pull_up>,
+				/* uart4_tx_m0 */
+				<1 RK_PB1 1 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart4m1_xfer: uart4m1-xfer {
+			rockchip,pins =
+				/* uart4_rx_m1 */
+				<1 RK_PC4 4 &pcfg_pull_up>,
+				/* uart4_tx_m1 */
+				<1 RK_PC5 4 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart4m1_ctsn: uart4m1-ctsn {
+			rockchip,pins =
+				/* uart4m1_ctsn */
+				<1 RK_PC7 4 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		uart4m1_rtsn: uart4m1-rtsn {
+			rockchip,pins =
+				/* uart4m1_rtsn */
+				<1 RK_PC6 4 &pcfg_pull_none>;
+		};
+	};
+
+	uart5 {
+		/omit-if-no-ref/
+		uart5m0_xfer: uart5m0-xfer {
+			rockchip,pins =
+				/* uart5_rx_m0 */
+				<3 RK_PA7 2 &pcfg_pull_up>,
+				/* uart5_tx_m0 */
+				<3 RK_PA6 2 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart5m0_ctsn: uart5m0-ctsn {
+			rockchip,pins =
+				/* uart5m0_ctsn */
+				<3 RK_PA5 2 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		uart5m0_rtsn: uart5m0-rtsn {
+			rockchip,pins =
+				/* uart5m0_rtsn */
+				<3 RK_PA4 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart5m1_xfer: uart5m1-xfer {
+			rockchip,pins =
+				/* uart5_rx_m1 */
+				<1 RK_PD2 4 &pcfg_pull_up>,
+				/* uart5_tx_m1 */
+				<1 RK_PD3 4 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart5m1_ctsn: uart5m1-ctsn {
+			rockchip,pins =
+				/* uart5m1_ctsn */
+				<1 RK_PD1 4 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		uart5m1_rtsn: uart5m1-rtsn {
+			rockchip,pins =
+				/* uart5m1_rtsn */
+				<1 RK_PD0 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart5m2_xfer: uart5m2-xfer {
+			rockchip,pins =
+				/* uart5_rx_m2 */
+				<3 RK_PD0 2 &pcfg_pull_up>,
+				/* uart5_tx_m2 */
+				<3 RK_PC7 2 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart5m2_ctsn: uart5m2-ctsn {
+			rockchip,pins =
+				/* uart5m2_ctsn */
+				<3 RK_PD2 2 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		uart5m2_rtsn: uart5m2-rtsn {
+			rockchip,pins =
+				/* uart5m2_rtsn */
+				<3 RK_PD1 2 &pcfg_pull_none>;
+		};
+	};
+
+	vicap {
+		/omit-if-no-ref/
+		vicapm0_pins: vicapm0-pins {
+			rockchip,pins =
+				/* vicap_clkin_m0 */
+				<3 RK_PC2 1 &pcfg_pull_none>,
+				/* vicap_d0_m0 */
+				<3 RK_PB0 1 &pcfg_pull_none>,
+				/* vicap_d1_m0 */
+				<3 RK_PB1 1 &pcfg_pull_none>,
+				/* vicap_d2_m0 */
+				<3 RK_PB2 1 &pcfg_pull_none>,
+				/* vicap_d3_m0 */
+				<3 RK_PB3 1 &pcfg_pull_none>,
+				/* vicap_d4_m0 */
+				<3 RK_PB4 1 &pcfg_pull_none>,
+				/* vicap_d5_m0 */
+				<3 RK_PB5 1 &pcfg_pull_none>,
+				/* vicap_d6_m0 */
+				<3 RK_PB6 1 &pcfg_pull_none>,
+				/* vicap_d7_m0 */
+				<3 RK_PB7 1 &pcfg_pull_none>,
+				/* vicap_d8_m0 */
+				<3 RK_PC0 1 &pcfg_pull_none>,
+				/* vicap_d9_m0 */
+				<3 RK_PC1 1 &pcfg_pull_none>,
+				/* vicap_hsync_m0 */
+				<3 RK_PC3 1 &pcfg_pull_none>,
+				/* vicap_vsync_m0 */
+				<3 RK_PC5 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		vicapm1_pins: vicapm1-pins {
+			rockchip,pins =
+				/* vicap_clkin_m1 */
+				<1 RK_PD0 2 &pcfg_pull_none>,
+				/* vicap_d0_m1 */
+				<1 RK_PA2 3 &pcfg_pull_none>,
+				/* vicap_d1_m1 */
+				<1 RK_PB1 4 &pcfg_pull_none>,
+				/* vicap_d2_m1 */
+				<1 RK_PC0 2 &pcfg_pull_none>,
+				/* vicap_d3_m1 */
+				<1 RK_PC1 2 &pcfg_pull_none>,
+				/* vicap_d4_m1 */
+				<1 RK_PC2 2 &pcfg_pull_none>,
+				/* vicap_d5_m1 */
+				<1 RK_PC3 2 &pcfg_pull_none>,
+				/* vicap_d6_m1 */
+				<1 RK_PC4 2 &pcfg_pull_none>,
+				/* vicap_d7_m1 */
+				<1 RK_PC5 2 &pcfg_pull_none>,
+				/* vicap_d8_m1 */
+				<1 RK_PC6 2 &pcfg_pull_none>,
+				/* vicap_d9_m1 */
+				<1 RK_PC7 2 &pcfg_pull_none>,
+				/* vicap_hsync_m1 */
+				<1 RK_PD1 2 &pcfg_pull_none>,
+				/* vicap_vsync_m1 */
+				<1 RK_PD2 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		vicap_d10: vicap-d10 {
+			rockchip,pins =
+				/* vicap_d10 */
+				<3 RK_PC6 1 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		vicap_d11: vicap-d11 {
+			rockchip,pins =
+				/* vicap_d11 */
+				<3 RK_PC7 1 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		vicap_d12: vicap-d12 {
+			rockchip,pins =
+				/* vicap_d12 */
+				<3 RK_PD0 1 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		vicap_d13: vicap-d13 {
+			rockchip,pins =
+				/* vicap_d13 */
+				<3 RK_PD1 1 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		vicap_d14: vicap-d14 {
+			rockchip,pins =
+				/* vicap_d14 */
+				<3 RK_PD2 1 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		vicap_d15: vicap-d15 {
+			rockchip,pins =
+				/* vicap_d15 */
+				<3 RK_PD3 1 &pcfg_pull_none>;
+		};
+	};
+};
+
+/*
+ * This part is edited handly.
+ */
+&pinctrl {
+	vicap {
+		/omit-if-no-ref/
+		vicap_clkout_m0: vicap-clkout-m0 {
+			rockchip,pins =
+				/* vicap_clkout_m0 */
+				<3 RK_PC4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		vicap_clkout_m1: vicap-clkout-m1 {
+			rockchip,pins =
+				/* vicap_clkout_m1 */
+				<1 RK_PD3 2 &pcfg_pull_none>;
+		};
+	};
+
+	mipi {
+		/omit-if-no-ref/
+		mipi_refclk_out0: mipi-refclk-out0 {
+			rockchip,pins =
+				/* mipi_refclk_out0 */
+				<3 RK_PC4 2 &pcfg_pull_none>;
+		};
+		/omit-if-no-ref/
+		mipi_refclk_out1: mipi-refclk-out1 {
+			rockchip,pins =
+				/* mipi_refclk_out1 */
+				<3 RK_PC6 3 &pcfg_pull_none>;
+		};
+	};
+
+	lcd {
+		/omit-if-no-ref/
+		bt1120_pins: bt1120-pins {
+			rockchip,pins =
+				/* lcd_clk */
+				<1 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d0 */
+				<1 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d1 */
+				<1 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d2 */
+				<1 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d3 */
+				<1 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d4 */
+				<1 RK_PC3 1 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d5 */
+				<1 RK_PC2 1 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d6 */
+				<1 RK_PC1 1 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d7 */
+				<1 RK_PC0 1 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d8 */
+				<2 RK_PA0 3 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d9 */
+				<2 RK_PA1 3 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d10 */
+				<2 RK_PA2 3 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d11 */
+				<2 RK_PA3 3 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d12 */
+				<2 RK_PA4 3 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d13 */
+				<2 RK_PA5 3 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d14 */
+				<2 RK_PA6 3 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d15 */
+				<2 RK_PA7 3 &pcfg_pull_none_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		bt656_pins: bt656-pins {
+			rockchip,pins =
+				/* lcd_clk */
+				<1 RK_PD3 1 &pcfg_pull_none_drv_level_2>,
+				/* lcd_d0 */
+				<1 RK_PC7 1 &pcfg_pull_none_drv_level_1>,
+				/* lcd_d1 */
+				<1 RK_PC6 1 &pcfg_pull_none_drv_level_1>,
+				/* lcd_d2 */
+				<1 RK_PC5 1 &pcfg_pull_none_drv_level_1>,
+				/* lcd_d3 */
+				<1 RK_PC4 1 &pcfg_pull_none_drv_level_1>,
+				/* lcd_d4 */
+				<1 RK_PC3 1 &pcfg_pull_none_drv_level_1>,
+				/* lcd_d5 */
+				<1 RK_PC2 1 &pcfg_pull_none_drv_level_1>,
+				/* lcd_d6 */
+				<1 RK_PC1 1 &pcfg_pull_none_drv_level_1>,
+				/* lcd_d7 */
+				<1 RK_PC0 1 &pcfg_pull_none_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		rgb3x8_pins: rgb3x8-pins {
+			rockchip,pins =
+				/* lcd_clk */
+				<1 RK_PD3 1 &pcfg_pull_none_drv_level_4>,
+				/* lcd_d0 */
+				<1 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d1 */
+				<1 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d2 */
+				<1 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d3 */
+				<1 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d4 */
+				<1 RK_PC3 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d5 */
+				<1 RK_PC2 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d6 */
+				<1 RK_PC1 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d7 */
+				<1 RK_PC0 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_den */
+				<1 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_hsync */
+				<1 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_vsync */
+				<1 RK_PD2 1 &pcfg_pull_none_drv_level_3>;
+		};
+
+		/omit-if-no-ref/
+		rgb565_pins: rgb565-pins {
+			rockchip,pins =
+				/* lcd_clk */
+				<1 RK_PD3 1 &pcfg_pull_none_drv_level_4>,
+				/* lcd_d0 */
+				<1 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d1 */
+				<1 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d2 */
+				<1 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d3 */
+				<1 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d4 */
+				<1 RK_PC3 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d5 */
+				<1 RK_PC2 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d6 */
+				<1 RK_PC1 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d7 */
+				<1 RK_PC0 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d8 */
+				<2 RK_PA0 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d9 */
+				<2 RK_PA1 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d10 */
+				<2 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d11 */
+				<2 RK_PA3 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d12 */
+				<2 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d13 */
+				<2 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d14 */
+				<2 RK_PA6 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_d15 */
+				<2 RK_PA7 3 &pcfg_pull_none_drv_level_3>,
+				/* lcd_den */
+				<1 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_hsync */
+				<1 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+				/* lcd_vsync */
+				<1 RK_PD2 1 &pcfg_pull_none_drv_level_3>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
new file mode 100644
index 000000000000..7b2e6142a103
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rockchip,rv1106-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	compatible = "rockchip,rv1106";
+
+	interrupt-parent = <&gic>;
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		gpio4 = &gpio4;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@f00 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0xf00>;
+			clocks = <&cru ARMCLK>;
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		clock-frequency = <24000000>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	xin24m: oscillator {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xin24m";
+		#clock-cells = <0>;
+	};
+
+	pinctrl: pinctrl {
+		compatible = "rockchip,rv1106-pinctrl";
+		rockchip,grf = <&gpio1_ioc>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gpio0: gpio@ff380000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0xff380000 0x100>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			rockchip,grf = <&gpio0_ioc>;
+		};
+
+		gpio1: gpio@ff530000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0xff530000 0x100>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 32 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			rockchip,grf = <&gpio1_ioc>;
+		};
+
+		gpio2: gpio@ff540000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0xff540000 0x100>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 64 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			rockchip,grf = <&gpio2_ioc>;
+		};
+
+		gpio3: gpio@ff550000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0xff550000 0x100>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 96 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			rockchip,grf = <&gpio3_ioc>;
+		};
+
+		gpio4: gpio@ff560000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0xff560000 0x100>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 128 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			rockchip,grf = <&gpio4_ioc>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		grf: syscon@ff000000 {
+			compatible = "rockchip,rv1106-grf", "syscon";
+			reg = <0xff000000 0x68000>;
+		};
+
+		gic: interrupt-controller@ff1f0000 {
+			compatible = "arm,gic-400";
+			reg = <0xff1f1000 0x1000>,
+			      <0xff1f2000 0x2000>,
+			      <0xff1f4000 0x2000>,
+			      <0xff1f6000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+		};
+
+		gpio0_ioc: syscon@ff388000 {
+			compatible = "rockchip,rv1106-gpio-ioc", "syscon";
+			reg = <0xff388000 0x8000>;
+		};
+
+		cru: clock-controller@ff3a0000 {
+			compatible = "rockchip,rv1106-cru";
+			reg = <0xff3a0000 0x20000>;
+			clocks = <&xin24m>;
+			clock-names = "xin24m";
+			rockchip,grf = <&grf>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		saradc: adc@ff3c0000 {
+			compatible = "rockchip,rv1106-saradc", "rockchip,rk3588-saradc";
+			reg = <0xff3c0000 0x100>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+			clock-names = "saradc", "apb_pclk";
+			#io-channel-cells = <1>;
+			status = "disabled";
+		};
+
+		uart0: serial@ff4a0000 {
+			compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+			reg = <0xff4a0000 0x100>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart1: serial@ff4b0000 {
+			compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+			reg = <0xff4b0000 0x100>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: serial@ff4c0000 {
+			compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+			reg = <0xff4c0000 0x100>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart3: serial@ff4d0000 {
+			compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+			reg = <0xff4d0000 0x100>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart4: serial@ff4e0000 {
+			compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+			reg = <0xff4e0000 0x100>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart5: serial@ff4f0000 {
+			compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+			reg = <0xff4f0000 0x100>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		gpio1_ioc: syscon@ff538000 {
+			compatible = "rockchip,rv1106-gpio-ioc", "syscon";
+			reg = <0xff538000 0x8000>;
+		};
+
+		gpio2_ioc: syscon@ff548000 {
+			compatible = "rockchip,rv1106-gpio-ioc", "syscon";
+			reg = <0xff548000 0x8000>;
+		};
+
+		gpio3_ioc: syscon@ff558000 {
+			compatible = "rockchip,rv1106-gpio-ioc", "syscon";
+			reg = <0xff558000 0x8000>;
+		};
+
+		gpio4_ioc: syscon@ff568000 {
+			compatible = "rockchip,rv1106-gpio-ioc", "syscon";
+			reg = <0xff568000 0x8000>;
+		};
+
+		wdt: watchdog@ff5a0000 {
+			compatible = "rockchip,rv1106-wdt", "snps,dw-wdt";
+			reg = <0xff5a0000 0x100>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
+			clock-names = "tclk", "pclk";
+			status = "disabled";
+		};
+
+		system_sram: sram@ff6c0000 {
+			compatible = "mmio-sram";
+			reg = <0xff6c0000 0x40000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xff6c0000 0x40000>;
+		};
+
+		emmc: mmc@ffa90000 {
+			compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
+			reg = <0xffa90000 0x4000>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>,
+				 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+			clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+			fifo-depth = <0x100>;
+			max-frequency = <200000000>;
+			status = "disabled";
+		};
+
+		sdmmc: mmc@ffaa0000 {
+			compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
+			reg = <0xffaa0000 0x4000>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>,
+				 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+			clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+			fifo-depth = <0x100>;
+			max-frequency = <200000000>;
+			status = "disabled";
+		};
+
+		sfc: spi@ffac0000 {
+			compatible = "rockchip,sfc";
+			reg = <0xffac0000 0x4000>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+			clock-names = "clk_sfc", "hclk_sfc";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+};
+
+#include "rv1106-pinctrl.dtsi"
-- 
2.43.0

[PATCH v2 5/6] dt-bindings: arm: rockchip: Add Luckfox Pico Mini B

[Simon Glass]

Add the compatible for the Luckfox Pico Mini B, a small board using
the Rockchip RV1103 with 64MB of in-package DDR2 and a 128MB SPI NAND.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

(no changes since v1)

 Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 1a9dde18626d..711029ee78af 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -813,6 +813,11 @@ properties:
           - const: netxeon,r89
           - const: rockchip,rk3288
 
+      - description: Luckfox Pico Mini B
+        items:
+          - const: luckfox,pico-mini-b
+          - const: rockchip,rv1103
+
       - description: Onion Omega4 Evaluation board
         items:
           - const: onion,omega4-evb
-- 
2.43.0

[PATCH v2 6/6] ARM: dts: rockchip: Add Luckfox Pico Mini B

[Simon Glass]

Add the devicetree for the Luckfox Pico Mini B, a small board using
the Rockchip RV1103 with 64MB of in-package DDR2, a 128MB Winbond SPI
NAND and a microSD slot. The console is on UART2.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

(no changes since v1)

 arch/arm/boot/dts/rockchip/Makefile           |  1 +
 .../rockchip/rv1103-luckfox-pico-mini-b.dts   | 93 +++++++++++++++++++
 2 files changed, 94 insertions(+)
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103-luckfox-pico-mini-b.dts

diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile
index d0154fd7ff24..62a2ed96dd9b 100644
--- a/arch/arm/boot/dts/rockchip/Makefile
+++ b/arch/arm/boot/dts/rockchip/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+	rv1103-luckfox-pico-mini-b.dtb \
 	rv1103b-omega4-evb.dtb \
 	rv1108-elgin-r1.dtb \
 	rv1108-evb.dtb \
diff --git a/arch/arm/boot/dts/rockchip/rv1103-luckfox-pico-mini-b.dts b/arch/arm/boot/dts/rockchip/rv1103-luckfox-pico-mini-b.dts
new file mode 100644
index 000000000000..287dbf1307e8
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1103-luckfox-pico-mini-b.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Luckfox Electronics Co., Ltd
+ */
+
+/dts-v1/;
+
+#include "rv1103.dtsi"
+
+/ {
+	model = "Luckfox Pico Mini B";
+	compatible = "luckfox,pico-mini-b", "rockchip,rv1103";
+
+	aliases {
+		mmc0 = &sdmmc;
+		serial2 = &uart2;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x04000000>;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
+	status = "okay";
+};
+
+&sfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&fspi_pins &fspi_cs0>;
+	status = "okay";
+
+	spi_nand: flash@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <75000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "env";
+				reg = <0x00000000 0x00040000>;
+			};
+
+			partition@40000 {
+				label = "idblock";
+				reg = <0x00040000 0x00100000>;
+				read-only;
+			};
+
+			partition@140000 {
+				label = "uboot";
+				reg = <0x00140000 0x00100000>;
+				read-only;
+			};
+
+			partition@240000 {
+				label = "boot";
+				reg = <0x00240000 0x00800000>;
+			};
+
+			partition@a40000 {
+				label = "ubi";
+				reg = <0x00a40000 0x075c0000>;
+			};
+		};
+	};
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2m1_xfer>;
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
-- 
2.43.0

Re: [PATCH v2 1/6] dt-bindings: clock: rockchip: Add RV1106 CRU support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The dt-bindings header defines clock IDs but omits all reset macros (e.g., SRST_*), despite the YAML schema explicitly requiring #reset-cells.
--

--- Patch [1]: [PATCH v2 1/6] dt-bindings: clock: rockchip: Add RV1106 CRU support ---
commit 6d501c2edd443b968951f83a3746f9eddc260735
Author: Simon Glass <sjg@chromium.org>

dt-bindings: clock: rockchip: Add RV1106 CRU support

This commit adds the clock binding header and schema for the Rockchip RV1106
clock and reset unit. The RV1103 package variant also uses this same CRU.

> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
> new file mode 100644
> index 0000000000000..b99dce9ff9356
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml

[ ... ]

> +required:
> +  - compatible
> +  - reg
> +  - "#clock-cells"
> +  - "#reset-cells"

[ ... ]

> diff --git a/include/dt-bindings/clock/rockchip,rv1106-cru.h b/include/dt-bindings/clock/rockchip,rv1106-cru.h
> new file mode 100644
> index 0000000000000..6b13e98b8d549
> --- /dev/null
> +++ b/include/dt-bindings/clock/rockchip,rv1106-cru.h

[ ... ]

> +/* mmc phase clocks */
> +#define SCLK_EMMC_DRV		278
> +#define SCLK_EMMC_SAMPLE	279
> +#define SCLK_SDMMC_DRV		280
> +#define SCLK_SDMMC_SAMPLE	281
> +#define SCLK_SDIO_DRV		282
> +#define SCLK_SDIO_SAMPLE	283
> +
> +#endif

[Severity: Low]
Since the YAML schema explicitly mandates "#reset-cells", should this header
also include the corresponding reset macro definitions (e.g., SRST_*)? 

Without these macros, device tree nodes consuming a reset from the RV1106 CRU
will be forced to hardcode numeric reset indices instead of using readable
names.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260714193656.2196447-1-sjg@chromium.org?part=1

Re: [PATCH v2 2/6] clk: rockchip: Add clock controller for the RV1106

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] The `RV1106_CPUCLK_RATE` macro unconditionally overwrites the dynamically calculated safe intermediate CPU divider during frequency transitions, causing CPU crashes.
- [High] The exported `PLL_APLL` clock is silently overwritten by anonymous clock branches due to a dummy ID collision.
- [High] Register collision between `CLK_RTC_32K` and `CLK_I2C1` multiplexers.
- [Medium] CLK_VICAP_M1_FRAC is missing the CLK_SET_RATE_PARENT flag.
--

--- Patch [2]: [PATCH v2 2/6] clk: rockchip: Add clock controller for the RV1106 ---
commit f23e8ffe0002c99e81093bf229093ffef3a65c00
Author: Simon Glass <sjg@chromium.org>

clk: rockchip: Add clock controller for the RV1106

The patch adds the clock and reset controller driver for the Rockchip
RV1106, based on the vendor kernel adapted to the upstream clock framework.
It also provides the MMC drive and sample phase clocks from the CRU via
an auxiliary GRF regmap.

Link: https://github.com/LuckfoxTECH/luckfox-pico

> diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c
> new file mode 100644
> index 0000000000000..cb21f32c8a26b
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk-rv1106.c
> @@ -0,0 +1,1100 @@

[ ... ]

> +#define RV1106_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg, _is_pvtpll)	\
> +{									\
> +	.prate = _prate,						\
> +	.divs = {							\
> +		RV1106_CLKSEL0(_aclk_core),				\
> +		RV1106_CLKSEL1(_pclk_dbg),				\
> +	},								\
> +	.pre_muxs = {							\
> +		RV1106_CLKSEL3(1),					\
> +		RV1106_CLKSEL2(2),					\
> +	},								\

[Severity: High]
Does this hardcoded array overwrite the safe intermediate divider calculated
by the generic CPU clock framework during frequency scaling?

The core clock framework calculates a safe intermediate divider and writes it
to RV1106_CORECLKSEL_CON(0) bits 4:0, as configured in rv1106_cpuclk_data:

	.core_reg[0] = RV1106_CORECLKSEL_CON(0),
	.div_core_shift[0] = 0,
	.div_core_mask[0] = 0x1f,

By unconditionally applying RV1106_CLKSEL3(1) in the pre_muxs array, could it
overwrite this dynamically calculated divider and potentially cause instability
during CPU frequency transitions?

[ ... ]

> +static struct rockchip_clk_branch rv1106_rtc32k_pmu_fracmux __initdata =
> +	MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
> +			RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS);

[Severity: High]
Are clk_rtc_32k and clk_i2c1 sharing the same register bitfield?

This multiplexer is defined using bits 6:7 of RV1106_PMUCLKSEL_CON(0).
However, later in rv1106_clk_branches, CLK_I2C1 is defined using the exact
same bits:

	COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_24m_32k_p, 0,
			RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS,

Could modifying the parent of one clock inadvertently corrupt the
configuration of the other?

[ ... ]

> +static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
> +
> +	FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
> +
> +	/* PD_CORE */
> +	GATE(CLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,

[Severity: High]
Will these anonymous branches using ID 0 silently overwrite the PLL_APLL
clock in the provider's clock array?

Since PLL_APLL corresponds to ID 0 in the DT bindings, it gets registered
first at ctx->clk_data.clks[0]. Since rockchip_clk_set_lookup() doesn't
ignore ID 0, do these dummy IDs cause device tree consumers of the APLL
clock to receive an incorrect internal anonymous clock instead?

[ ... ]

> +	COMPOSITE(CLK_VICAP_M1_SRC, "clk_vicap_m1_src", mux_gpll_cpll_p, 0,
> +			RV1106_CLKSEL_CON(31), 7, 1, MFLAGS, 2, 5, DFLAGS,
> +			RV1106_CLKGATE_CON(3), 13, GFLAGS),
> +	COMPOSITE_FRACMUX(CLK_VICAP_M1_FRAC, "clk_vicap_m1_frac", "clk_vicap_m1_src", 0,
> +			RV1106_CLKSEL_CON(32), 0,
> +			RV1106_CLKGATE_CON(3), 14, GFLAGS,
> +			&rv1106_clk_vicap_m1_fracmux),

[Severity: Medium]
Should CLK_VICAP_M1_FRAC pass the CLK_SET_RATE_PARENT flag instead of 0?

Its sibling CLK_VICAP_M0_FRAC uses CLK_SET_RATE_PARENT to allow rate changes
to propagate up to the integer divider. Without this flag, will the clock
framework fail to adjust the parent divider when a rate change is requested?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260714193656.2196447-1-sjg@chromium.org?part=2

Re: [PATCH v2 4/6] ARM: dts: rockchip: Add support for RV1106 and RV1103

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The DT defines distributed IOC blocks for each GPIO bank via `rockchip,grf` properties, which violates the upstream dt-binding schema and causes register corruption due to driver mismatch.
- [Medium] The device tree relies on the 'rockchip,rv1106-pinctrl' compatible string, which is entirely unsupported by the upstream pinctrl-rockchip driver and violates the dt-binding schema.
--

--- Patch [4]: [PATCH v2 4/6] ARM: dts: rockchip: Add support for RV1106 and RV1103 ---
commit e0d1bbbfe5826e8f7c17c9a0008a5c218538f589
Author: Simon Glass <sjg@chromium.org>

ARM: dts: rockchip: Add support for RV1106 and RV1103

Add the devicetree files for the Rockchip RV1106 and its RV1103 package
variant. The pinctrl data comes from the vendor kernel in the Luckfox Pico
SDK.

Link: https://github.com/LuckfoxTECH/luckfox-pico

> diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
> new file mode 100644
> index 0000000000000..7b2e6142a103f
> --- /dev/null
> +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
> @@ -0,0 +1,321 @@
[ ... ]
> +	pinctrl: pinctrl {
> +		compatible = "rockchip,rv1106-pinctrl";

[Severity: Medium]
Does this compatible string have accompanying dt-binding schema and driver
support? The 'rockchip,rv1106-pinctrl' string appears to be missing from the
upstream device tree schema and pinctrl driver, which could cause dtbs_check
validation failures and prevent the driver from probing.

> +		rockchip,grf = <&gpio1_ioc>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		gpio0: gpio@ff380000 {
> +			compatible = "rockchip,gpio-bank";
> +			reg = <0xff380000 0x100>;
> +			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pinctrl 0 0 32>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			rockchip,grf = <&gpio0_ioc>;

[Severity: High]
Will the upstream pinctrl-rockchip driver parse these bank-specific syscons
properly? The upstream driver typically only parses the parent pinctrl node's
rockchip,grf property.

Could this cause register corruption when configuring pins? Since the parent
pinctrl node points to gpio1_ioc, the driver might use gpio1_ioc for all
banks. This would silently overwrite gpio1_ioc registers when attempting to
configure pins for other banks like gpio0 or gpio2.

Also, does adding the rockchip,grf property to the gpio-bank child nodes
violate the rockchip,gpio-bank.yaml schema which forbids additional
properties?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260714193656.2196447-1-sjg@chromium.org?part=4

Re: [PATCH v2 5/6] dt-bindings: arm: rockchip: Add Luckfox Pico Mini B

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The compatible string block for 'Luckfox Pico Mini B' is inserted out of alphabetical order.
--

--- Patch [5]: [PATCH v2 5/6] dt-bindings: arm: rockchip: Add Luckfox Pico Mini B ---
commit 61521ad6f3be156c0a561b23d28c5db096f06212
Author: Simon Glass <sjg@chromium.org>

dt-bindings: arm: rockchip: Add Luckfox Pico Mini B

This commit adds the device tree binding compatible strings for the
Luckfox Pico Mini B board, which is based on the Rockchip RV1103 SoC.

> diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
> index 1a9dde18626d0..711029ee78af2 100644
> --- a/Documentation/devicetree/bindings/arm/rockchip.yaml
> +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
> @@ -813,6 +813,11 @@ properties:
>            - const: netxeon,r89
>            - const: rockchip,rk3288
>  
> +      - description: Luckfox Pico Mini B
> +        items:
> +          - const: luckfox,pico-mini-b
> +          - const: rockchip,rv1103
> +

[Severity: Low]
This isn't a bug, but is this new block inserted out of alphabetical order?

The file generally maintains entries alphabetically by vendor prefix.
Should this luckfox entry be placed alongside the other luckfox entries
higher up in the file, rather than here between netxeon and onion?

>        - description: Onion Omega4 Evaluation board
>          items:
>            - const: onion,omega4-evb

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260714193656.2196447-1-sjg@chromium.org?part=5