* [PATCH] dt-bindings: clock: ti,da850-pll: Convert to DT schema
@ 2026-07-17 18:21 Bhargav Joshi
2026-07-17 18:28 ` sashiko-bot
0 siblings, 1 reply; 2+ messages in thread
From: Bhargav Joshi @ 2026-07-17 18:21 UTC (permalink / raw)
To: David Lechner, Michael Turquette, Stephen Boyd, Brian Masney,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-clk, devicetree, linux-kernel, goledhruva, m-chawdhry,
daniel.baluta, simona.toaca, j.bhargav.u
Convert TI da850-pll binding from legacy text to dt schema.
No functional change is introduced during conversion.
Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
---
.../devicetree/bindings/clock/ti/davinci/pll.txt | 96 -----------
.../bindings/clock/ti/davinci/ti,da850-pll.yaml | 177 +++++++++++++++++++++
2 files changed, 177 insertions(+), 96 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt
deleted file mode 100644
index c9894538315b..000000000000
--- a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt
+++ /dev/null
@@ -1,96 +0,0 @@
-Binding for TI DaVinci PLL Controllers
-
-The PLL provides clocks to most of the components on the SoC. In addition
-to the PLL itself, this controller also contains bypasses, gates, dividers,
-an multiplexers for various clock signals.
-
-Required properties:
-- compatible: shall be one of:
- - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
- - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
-- reg: physical base address and size of the controller's register area.
-- clocks: phandles corresponding to the clock names
-- clock-names: names of the clock sources - depends on compatible string
- - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
- - for "ti,da850-pll1", shall be "clksrc"
-
-Optional properties:
-- ti,clkmode-square-wave: Indicates that the board is supplying a square
- wave input on the OSCIN pin instead of using a crystal oscillator.
- This property is only valid when compatible = "ti,da850-pll0".
-
-
-Optional child nodes:
-
-pllout
- Describes the main PLL clock output (before POSTDIV). The node name must
- be "pllout".
-
- Required properties:
- - #clock-cells: shall be 0
-
-sysclk
- Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
- domains. The node name must be "sysclk". Consumers of this node should
- use "n" in "SYSCLKn" as the index parameter for the clock cell.
-
- Required properties:
- - #clock-cells: shall be 1
-
-auxclk
- Describes the AUXCLK output of the PLL. The node name must be "auxclk".
- This child node is only valid when compatible = "ti,da850-pll0".
-
- Required properties:
- - #clock-cells: shall be 0
-
-obsclk
- Describes the OBSCLK output of the PLL. The node name must be "obsclk".
-
- Required properties:
- - #clock-cells: shall be 0
-
-
-Examples:
-
- pll0: clock-controller@11000 {
- compatible = "ti,da850-pll0";
- reg = <0x11000 0x1000>;
- clocks = <&ref_clk>, <&pll1_sysclk 3>;
- clock-names = "clksrc", "extclksrc";
- ti,clkmode-square-wave;
-
- pll0_pllout: pllout {
- #clock-cells = <0>;
- };
-
- pll0_sysclk: sysclk {
- #clock-cells = <1>;
- };
-
- pll0_auxclk: auxclk {
- #clock-cells = <0>;
- };
-
- pll0_obsclk: obsclk {
- #clock-cells = <0>;
- };
- };
-
- pll1: clock-controller@21a000 {
- compatible = "ti,da850-pll1";
- reg = <0x21a000 0x1000>;
- clocks = <&ref_clk>;
- clock-names = "clksrc";
-
- pll0_sysclk: sysclk {
- #clock-cells = <1>;
- };
-
- pll0_obsclk: obsclk {
- #clock-cells = <0>;
- };
- };
-
-Also see:
-- Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml b/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml
new file mode 100644
index 000000000000..5e4109567b75
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti/davinci/ti,da850-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI DaVinci PLL Controllers
+
+maintainers:
+ - David Lechner <david@lechnology.com>
+ - Bhargav Joshi <j.bhargav.u@gmail.com>
+
+description:
+ The PLL provides clocks to most of the components on the SoC. In addition to
+ the PLL itself, this controller also contains bypasses, gates, dividers, an
+ multiplexers for various clock signals.
+
+properties:
+ compatible:
+ enum:
+ - ti,da850-pll0
+ - ti,da850-pll1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+ ti,clkmode-square-wave:
+ type: boolean
+ description:
+ Indicates that the board is supplying a square wave input on the OSCIN
+ pin instead of using a crystal oscillator.
+
+ pllout:
+ type: object
+ description:
+ Main PLL clock output before POSTDIV.
+
+ properties:
+ '#clock-cells':
+ const: 0
+
+ required:
+ - '#clock-cells'
+
+ additionalProperties: false
+
+ sysclk:
+ type: object
+ description:
+ PLLDIVn divider clocks that provide the SYSCLKn clock domains. Consumers
+ of this node should use "n" in "SYSCLKn" as the index parameter for the
+ clock cell.
+
+ properties:
+ '#clock-cells':
+ const: 1
+
+ required:
+ - '#clock-cells'
+
+ additionalProperties: false
+
+ auxclk:
+ type: object
+ description:
+ AUXCLK output of the PLL
+
+ properties:
+ '#clock-cells':
+ const: 0
+
+ required:
+ - '#clock-cells'
+
+ additionalProperties: false
+
+ obsclk:
+ type: object
+ description:
+ the OBSCLK output of the PLL.
+
+ properties:
+ '#clock-cells':
+ const: 0
+
+ required:
+ - '#clock-cells'
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: ti,da850-pll0
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Primary reference clock input
+ - description: External clock source
+ clock-names:
+ items:
+ - const: clksrc
+ - const: extclksrc
+
+ - if:
+ properties:
+ compatible:
+ const: ti,da850-pll1
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ items:
+ - const: clksrc
+ ti,clkmode-square-wave: false
+ auxclk: false
+
+examples:
+ - |
+ clock-controller@11000 {
+ compatible = "ti,da850-pll0";
+ reg = <0x11000 0x1000>;
+ clocks = <&ref_clk>, <&pll1_sysclk 3>;
+ clock-names = "clksrc", "extclksrc";
+ ti,clkmode-square-wave;
+
+ pllout {
+ #clock-cells = <0>;
+ };
+
+ sysclk {
+ #clock-cells = <1>;
+ };
+
+ auxclk {
+ #clock-cells = <0>;
+ };
+
+ obsclk {
+ #clock-cells = <0>;
+ };
+ };
+
+ - |
+ clock-controller@21a000 {
+ compatible = "ti,da850-pll1";
+ reg = <0x21a000 0x1000>;
+ clocks = <&ref_clk>;
+ clock-names = "clksrc";
+
+ sysclk {
+ #clock-cells = <1>;
+ };
+
+ obsclk {
+ #clock-cells = <0>;
+ };
+ };
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260630-ti-pll-94f8eb9918c8
Best regards,
--
Bhargav
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] dt-bindings: clock: ti,da850-pll: Convert to DT schema
2026-07-17 18:21 [PATCH] dt-bindings: clock: ti,da850-pll: Convert to DT schema Bhargav Joshi
@ 2026-07-17 18:28 ` sashiko-bot
0 siblings, 0 replies; 2+ messages in thread
From: sashiko-bot @ 2026-07-17 18:28 UTC (permalink / raw)
To: Bhargav Joshi; +Cc: conor+dt, devicetree, robh
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The device tree schema example contains undefined phandle references (`&ref_clk` and `&pll1_sysclk`), which causes `dt_binding_check` to fail with compilation errors.
- [Medium] The schema fails to enforce strict bounds on `clocks` and `clock-names` inside conditional blocks, allowing invalid configurations to pass validation.
--
--- Patch [1]: [PATCH] dt-bindings: clock: ti,da850-pll: Convert to DT schema ---
commit d9fe4826c7bdb546d8ecd3e9ca8ac0454b95166c
Author: Bhargav Joshi <j.bhargav.u@gmail.com>
dt-bindings: clock: ti,da850-pll: Convert to DT schema
Convert TI da850-pll binding from legacy text to dt schema.
No functional change is introduced during conversion.
> diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml b/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml
> new file mode 100644
> index 0000000000000..5e4109567b75d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml
[ ... ]
> @@ -0,0 +1,177 @@
[ ... ]
> +allOf:
> + - if:
> + properties:
> + compatible:
> + const: ti,da850-pll0
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Primary reference clock input
> + - description: External clock source
[Severity: Medium]
Since the global clocks property specifies minItems: 1 and maxItems: 2, does
this ti,da850-pll0 block also need minItems: 2?
Without it, a device tree node with only 1 clock could silently pass validation
by falling back to the global limits.
> + clock-names:
> + items:
> + - const: clksrc
> + - const: extclksrc
> +
> + - if:
> + properties:
> + compatible:
> + const: ti,da850-pll1
> + then:
> + properties:
> + clocks:
> + maxItems: 1
> + clock-names:
> + items:
> + - const: clksrc
[Severity: Medium]
Does this block need maxItems: 1 for clock-names?
Since the global clock-names property allows maxItems: 2, a node with two
clock-names might pass validation for the ti,da850-pll1 variant.
> + ti,clkmode-square-wave: false
> + auxclk: false
> +
> +examples:
> + - |
> + clock-controller@11000 {
> + compatible = "ti,da850-pll0";
> + reg = <0x11000 0x1000>;
> + clocks = <&ref_clk>, <&pll1_sysclk 3>;
[Severity: Medium]
Will this cause make dt_binding_check to fail?
The &ref_clk and &pll1_sysclk phandles are not defined in this example, which
usually causes dtc compilation errors (Reference to non-existent node or label)
during validation workflows.
> + clock-names = "clksrc", "extclksrc";
> + ti,clkmode-square-wave;
[ ... ]
> + - |
> + clock-controller@21a000 {
> + compatible = "ti,da850-pll1";
> + reg = <0x21a000 0x1000>;
> + clocks = <&ref_clk>;
[Severity: Medium]
Similar to the first example, this references &ref_clk without defining it.
Could this lead to a dtc compilation error during make dt_binding_check?
> + clock-names = "clksrc";
> +
> + sysclk {
> + #clock-cells = <1>;
> + };
> +
> + obsclk {
> + #clock-cells = <0>;
> + };
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-ti-pll-v1-1-f6f9ba8c9b5e@gmail.com?part=1
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2026-07-17 18:28 ` sashiko-bot
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