Re: [PATCH v5 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Uninitialized hardware state (missing clock enablement & reset sequence violation) due to motorcomm PHY driver not handling clocks.
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--- Patch [2]: [PATCH v5 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO ---
commit c0855ea5f59329ce1c87ee05212dc9c8bf0d2728
Author: Jiaxing Hu <gahing@gahingwoo.com>

arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

This patch adds device tree support for the Rockchip RK3576 based
ArmSoM CM5 compute module and its CM5-IO carrier board. It configures
the GMAC0 Ethernet with an on-module MotorComm YT8531 PHY.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi
> new file mode 100644
> index 0000000000000..b6977b973b340
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi
[ ... ]
> +&mdio0 {
> +	reset-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
> +	reset-delay-us = <20000>;
> +	reset-post-delay-us = <100000>;
> +
> +	rgmii_phy0: phy@1 {
> +		compatible = "ethernet-phy-id4f51.e91b",
> +			     "ethernet-phy-ieee802.3-c22";
> +		reg = <0x1>;
> +		clocks = <&cru REFCLKO25M_GMAC0_OUT>;
> +	};
> +};

[Severity: High]
The commit message states that the REFCLKO25M_GMAC0_OUT clock is enabled by
the PHY driver. Does the motorcomm PHY driver actually handle clocks?

Looking at drivers/net/phy/motorcomm.c, there don't appear to be any calls to
clk_get() or devm_clk_get() to fetch and enable the clocks specified in the
device tree.

Additionally, dwmac-rk.c only fetches a PHY clock if the phy-is-integrated
property is present, which is missing here.

Because the MDIO bus deasserts the reset-gpios before the PHY device is
probed, will the PHY be brought out of reset with a dead clock?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260719034611.3623066-1-gahing@gahingwoo.com?part=2