[PATCH 0/2] arm64: dts: imx8qm: add smmu information for usb and add hsic usb port

[PATCH 0/2] arm64: dts: imx8qm: add smmu information for usb and add hsic usb port

[Frank.Li]

Add smmu information for usb and add hsic usb port.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Frank Li (2):
      arm64: dts: imx8qm-ss-conn: add usbotg3 iommu information
      arm64: dts: imx8qm-ss-conn: Add HSIC usb@5b0e0000 node

 arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)
---
base-commit: 3fe08b9796f36ef437ab9328e7dd1e5ff2d66603
change-id: 20260720-qm_smmu-417e915cb713

Best regards,
--  
Frank Li <Frank.Li@nxp.com>

[PATCH 1/2] arm64: dts: imx8qm-ss-conn: add usbotg3 iommu information

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>

Add usbotg3 iommu information.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
index ccf9f510e0f88..1370a571153a5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
@@ -32,3 +32,7 @@ &usdhc3 {
 	compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 	iommus = <&smmu 0x11 0x7f80>;
 };
+
+&usbotg3_cdns3 {
+	iommus = <&smmu 0x4 0x7f80>;
+};

-- 
2.43.0

[PATCH 2/2] arm64: dts: imx8qm-ss-conn: Add HSIC usb@5b0e0000 node

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>

Add usb@5b0e0000 and related node for i.MX8QM.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi | 34 +++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
index 1370a571153a5..c7063aaac4a34 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
@@ -4,6 +4,40 @@
  *	Dong Aisheng <aisheng.dong@nxp.com>
  */
 
+&{/} {
+	usbphynop2: usbphynop2 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&usb2_lpcg IMX_LPCG_CLK_7>;
+		clock-names = "main_clk";
+		power-domains = <&pd IMX_SC_R_USB_0_PHY>;
+		status = "disabled";
+	};
+};
+
+&conn_subsys {
+	usbh1: usb@5b0e0000 {
+		compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
+		reg = <0x5b0e0000 0x200>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+		phy_type = "hsic";
+		dr_mode = "host";
+		clocks = <&usb2_lpcg IMX_LPCG_CLK_6>;
+		ahb-burst-config = <0x0>;
+		tx-burst-size-dword = <0x10>;
+		rx-burst-size-dword = <0x10>;
+		power-domains = <&pd IMX_SC_R_USB_1>;
+		fsl,usbphy = <&usbphynop2>;
+		fsl,usbmisc = <&usbmisc2 0>;
+	};
+
+	usbmisc2: usbmisc@5b0e0200 {
+		compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+		#index-cells = <1>;
+		reg = <0x5b0e0200 0x200>;
+	};
+};
+
 &usbphy1 {
 	compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy";
 };

-- 
2.43.0

Re: [PATCH 2/2] arm64: dts: imx8qm-ss-conn: Add HSIC usb@5b0e0000 node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The `usbphynop2` node requests the wrong power domain (`IMX_SC_R_USB_0_PHY` instead of `IMX_SC_R_USB_1_PHY`).
- [Medium] The `usbh1` node is enabled by default (missing `status = "disabled";`), violating SoC `.dtsi` practices and causing unconditional probing.
- [Low] Missing required `#phy-cells` property in the `usbphynop2` node.
--

--- Patch [2]: [PATCH 2/2] arm64: dts: imx8qm-ss-conn: Add HSIC usb@5b0e0000 node ---
commit 9497d73ee79f69a11e0a9347cd596ca4c9842914
Author: Frank Li <Frank.Li@nxp.com>

arm64: dts: imx8qm-ss-conn: Add HSIC usb@5b0e0000 node

Add usb@5b0e0000 and related node for i.MX8QM.

> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
> index 1370a571153a5..c7063aaac4a34 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
> @@ -4,6 +4,40 @@
>   *	Dong Aisheng <aisheng.dong@nxp.com>
>   */
>  
> +&{/} {
> +	usbphynop2: usbphynop2 {
> +		compatible = "usb-nop-xceiv";

[Severity: Low]
Does this node need a #phy-cells = <0>; property?  The usb-nop-xceiv.yaml
binding schema typically requires this property to be present, and omitting
it might cause dtbs_check validation failures during the build.

> +		clocks = <&usb2_lpcg IMX_LPCG_CLK_7>;
> +		clock-names = "main_clk";
> +		power-domains = <&pd IMX_SC_R_USB_0_PHY>;

[Severity: High]
Is IMX_SC_R_USB_0_PHY the correct power domain for usbphynop2?  Since this is
for the USB_1 controller (usbh1), should this be IMX_SC_R_USB_1_PHY instead?

If it requests the USB_0 PHY domain, the USB_1 PHY hardware might remain
unpowered, causing the HSIC port to fail.

> +		status = "disabled";
> +	};
> +};
> +
> +&conn_subsys {
> +	usbh1: usb@5b0e0000 {
> +		compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
> +		reg = <0x5b0e0000 0x200>;

[Severity: Medium]
Should this node include a status = "disabled"; property?  Without it, the
usbh1 node is enabled by default and will probe unconditionally on all i.MX8QM
boards, even if the hardware interface isn't wired up.

Since the required usbphynop2 PHY is disabled, the controller might fail to
initialize, leading to boot delays and unnecessary resource allocation.

> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260720-qm_smmu-v1-0-3689fbd8b516@nxp.com?part=2

Re: [PATCH 1/2] arm64: dts: imx8qm-ss-conn: add usbotg3 iommu information

[Alexander Stein]

Hi Frank,

Am Montag, 20. Juli 2026, 23:10:33 CEST schrieb Frank.Li@oss.nxp.com:
> From: Frank Li <Frank.Li@nxp.com>
> 
> Add usbotg3 iommu information.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
> index ccf9f510e0f88..1370a571153a5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
> @@ -32,3 +32,7 @@ &usdhc3 {
>  	compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
>  	iommus = <&smmu 0x11 0x7f80>;
>  };
> +
> +&usbotg3_cdns3 {
> +	iommus = <&smmu 0x4 0x7f80>;

Where in the RM can you get these values?

Thanks and best regards,
Alexander

> +};
> 
> 


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH 1/2] arm64: dts: imx8qm-ss-conn: add usbotg3 iommu information

[Frank Li]

On Tue, Jul 21, 2026 at 09:48:16AM +0200, Alexander Stein wrote:
> Hi Frank,
>
> Am Montag, 20. Juli 2026, 23:10:33 CEST schrieb Frank.Li@oss.nxp.com:
> > From: Frank Li <Frank.Li@nxp.com>
> >
> > Add usbotg3 iommu information.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
> > index ccf9f510e0f88..1370a571153a5 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
> > @@ -32,3 +32,7 @@ &usdhc3 {
> >  	compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
> >  	iommus = <&smmu 0x11 0x7f80>;
> >  };
> > +
> > +&usbotg3_cdns3 {
> > +	iommus = <&smmu 0x4 0x7f80>;
>
> Where in the RM can you get these values?

0x4 is stream ID, any value between 0-31, uboot will use this value to
config stream ID for bus master by scfw API

0x7f80 means tire some bit to high before pass to smmu by hardware.
I don't think signal defination can be found at public documents.

static int arm_smmu_of_xlate(struct device *dev,
                             const struct of_phandle_args *args)
{
        u32 mask, fwid = 0;

        if (args->args_count > 0)
                fwid |= FIELD_PREP(ARM_SMMU_SMR_ID, args->args[0]);

        if (args->args_count > 1)
                fwid |= FIELD_PREP(ARM_SMMU_SMR_MASK, args->args[1]);
}

Frank

>
> Thanks and best regards,
> Alexander
>
> > +};
> >
> >
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-group.com/
>
>