* [PATCH] ARM: dts: allwinner: a10: Fix PMU interrupt
@ 2026-07-20 21:51 Andre Przywara
2026-07-22 17:29 ` Chen-Yu Tsai
0 siblings, 1 reply; 2+ messages in thread
From: Andre Przywara @ 2026-07-20 21:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland
Cc: devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
The Performance Monitoring Unit of the Cortex-A8 cores in the Allwinner
A10 SoC is connected to interrupt line 66, not 3. This is shown in the
manual (where interrupt 3 is assigned to UART2, also in our .dtsi), but
has also been confirmed by triggering an PMU overflow interrupt and
inspecting the IRQ controller status registers (from U-Boot).
Please note that "perf stat" does not use interrupts, this might explain
why this evaded the initial testing.
Fixes: 7e345d25c796 ("ARM: dts: sun4i-a10: Add PMU node")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/boot/dts/allwinner/sun4i-a10.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi
index 51a6464aab9a3..cabf619c2e217 100644
--- a/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi
@@ -185,7 +185,7 @@ de: display-engine {
pmu {
compatible = "arm,cortex-a8-pmu";
- interrupts = <3>;
+ interrupts = <66>;
};
reserved-memory {
--
2.46.4
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] ARM: dts: allwinner: a10: Fix PMU interrupt
2026-07-20 21:51 [PATCH] ARM: dts: allwinner: a10: Fix PMU interrupt Andre Przywara
@ 2026-07-22 17:29 ` Chen-Yu Tsai
0 siblings, 0 replies; 2+ messages in thread
From: Chen-Yu Tsai @ 2026-07-22 17:29 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec,
Samuel Holland, Andre Przywara
Cc: devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
On Mon, 20 Jul 2026 23:51:28 +0200, Andre Przywara wrote:
> The Performance Monitoring Unit of the Cortex-A8 cores in the Allwinner
> A10 SoC is connected to interrupt line 66, not 3. This is shown in the
> manual (where interrupt 3 is assigned to UART2, also in our .dtsi), but
> has also been confirmed by triggering an PMU overflow interrupt and
> inspecting the IRQ controller status registers (from U-Boot).
> Please note that "perf stat" does not use interrupts, this might explain
> why this evaded the initial testing.
>
> [...]
Applied to sunxi/dt-for-7.3 in sunxi, thanks!
[1/1] ARM: dts: allwinner: a10: Fix PMU interrupt
https://git.kernel.org/sunxi/linux/c/eb7051f75646
Best regards,
--
Chen-Yu Tsai <wens@kernel.org>
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