[PATCH 0/3] Power: Add power domain for A9

[PATCH 0/3] Power: Add power domain for A9

[Xianwei Zhao via B4 Relay]

Add power controller driver support for Amlogic A9 SoC.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Xianwei Zhao (3):
      dt-bindings: power: Add Amlogic A9 power domains
      pmdomain: amlogic: Add support for A9 power domains controller
      arm64: dts: amlogic: a9: Add power domain controller node

 .../bindings/power/amlogic,meson-sec-pwrc.yaml     |  1 +
 arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi        | 10 ++++
 drivers/pmdomain/amlogic/meson-secure-pwrc.c       | 69 ++++++++++++++++++++++
 include/dt-bindings/power/amlogic,a9-pwrc.h        | 61 +++++++++++++++++++
 4 files changed, 141 insertions(+)
---
base-commit: 544455a3a844edd6107b15cd0ab0b657399f2d49
change-id: 20260722-a9-pm-3efb3f2a4d72

Best regards,
-- 
Xianwei Zhao <xianwei.zhao@amlogic.com>

[PATCH 1/3] dt-bindings: power: Add Amlogic A9 power domains

[Xianwei Zhao via B4 Relay]

From: Xianwei Zhao <xianwei.zhao@amlogic.com>

Add devicetree binding document and related header file for
Amlogic A9 secure power domains.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
 .../bindings/power/amlogic,meson-sec-pwrc.yaml     |  1 +
 include/dt-bindings/power/amlogic,a9-pwrc.h        | 61 ++++++++++++++++++++++
 2 files changed, 62 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
index 12b71688dd34..e608a0c75961 100644
--- a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
@@ -22,6 +22,7 @@ properties:
       - amlogic,meson-s4-pwrc
       - amlogic,a4-pwrc
       - amlogic,a5-pwrc
+      - amlogic,a9-pwrc
       - amlogic,c3-pwrc
       - amlogic,t7-pwrc
       - amlogic,s6-pwrc
diff --git a/include/dt-bindings/power/amlogic,a9-pwrc.h b/include/dt-bindings/power/amlogic,a9-pwrc.h
new file mode 100644
index 000000000000..c1c2308a0d0c
--- /dev/null
+++ b/include/dt-bindings/power/amlogic,a9-pwrc.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2026 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_A9_POWER_H
+#define _DT_BINDINGS_AMLOGIC_A9_POWER_H
+
+#define PWRC_A9_DSPA_ID			0
+#define PWRC_A9_U3HSG_U3_ID		1
+#define PWRC_A9_DP_ID			2
+#define PWRC_A9_DOS_HCODEC_ID		3
+#define PWRC_A9_TAHOE_ID		4
+#define PWRC_A9_DOS_HEVC_ID		5
+#define PWRC_A9_U2H_ID			6
+#define PWRC_A9_U3DRD_B_ID		7
+#define PWRC_A9_VPU_HDMI_ID		8
+#define PWRC_A9_U2DRD_ID		9
+#define PWRC_A9_U3DRD_A_ID		10
+#define PWRC_A9_SD_EMMC_C_ID		11
+#define PWRC_A9_GE2D_ID			12
+#define PWRC_A9_AMFC_ID			13
+#define PWRC_A9_EDPTX_ID		14
+#define PWRC_A9_OPP_ID			15
+#define PWRC_A9_VICP_ID			16
+#define PWRC_A9_SD_EMMC_A_ID		17
+#define PWRC_A9_SD_EMMC_B_ID		18
+#define PWRC_A9_ETH_ID			19
+#define PWRC_A9_PCIE_A_ID		20
+#define PWRC_A9_PCIE_B_ID		21
+#define PWRC_A9_NNA_4T_ID		22
+#define PWRC_A9_HDMIRX_ID		23
+#define PWRC_A9_CVE_ID			24
+#define PWRC_A9_ISP_ID			25
+#define PWRC_A9_ETH_1G_ID		26
+#define PWRC_A9_U3HSG_HSG_ID		27
+#define PWRC_A9_U3DPPHY_U3_ID		28
+#define PWRC_A9_U3DPPHY_DP_ID		29
+#define PWRC_A9_PCIE3PHY_ID		30
+#define PWRC_A9_U3HSG_PCIE2_ID		31
+#define PWRC_A9_MALI_TOP_ID		32
+#define PWRC_A9_AO_SED_ID		33
+#define PWRC_A9_AO_IR_ID		34
+#define PWRC_A9_AO_UART_B_ID		35
+#define PWRC_A9_AO_UART_C_ID		36
+#define PWRC_A9_AO_UART_D_ID		37
+#define PWRC_A9_AO_SPISG_ID		38
+#define PWRC_A9_AO_UART_E_ID		39
+#define PWRC_A9_AO_CEC_ID		40
+#define PWRC_A9_EE_SRAMA_ID		41
+#define PWRC_A9_AUDIO_ID		42
+#define PWRC_A9_DMC0_ID			43
+#define PWRC_A9_GIC_ID			44
+#define PWRC_A9_DDRPHY_ID		45
+#define PWRC_A9_AUCPU_ID		46
+#define PWRC_A9_DSI0_ID			47
+#define PWRC_A9_DSI1_ID			48
+#define PWRC_A9_CAN0_ID			49
+#define PWRC_A9_CAN1_ID			50
+
+#endif

-- 
2.52.0

[PATCH 2/3] pmdomain: amlogic: Add support for A9 power domains controller

[Xianwei Zhao via B4 Relay]

From: Xianwei Zhao <xianwei.zhao@amlogic.com>

Add support for the A9 power controller, whose registers are
in the secure domain and should be accessed via SMC.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
 drivers/pmdomain/amlogic/meson-secure-pwrc.c | 69 ++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/drivers/pmdomain/amlogic/meson-secure-pwrc.c b/drivers/pmdomain/amlogic/meson-secure-pwrc.c
index 1d2f371d2d7f..133549956efa 100644
--- a/drivers/pmdomain/amlogic/meson-secure-pwrc.c
+++ b/drivers/pmdomain/amlogic/meson-secure-pwrc.c
@@ -16,6 +16,7 @@
 #include <dt-bindings/power/amlogic,t7-pwrc.h>
 #include <dt-bindings/power/amlogic,a4-pwrc.h>
 #include <dt-bindings/power/amlogic,a5-pwrc.h>
+#include <dt-bindings/power/amlogic,a9-pwrc.h>
 #include <dt-bindings/power/amlogic,s6-pwrc.h>
 #include <dt-bindings/power/amlogic,s7-pwrc.h>
 #include <dt-bindings/power/amlogic,s7d-pwrc.h>
@@ -175,6 +176,65 @@ static const struct meson_secure_pwrc_domain_desc a5_pwrc_domains[] = {
 	SEC_PD(A5_DSPA,		0),
 };
 
+static const struct meson_secure_pwrc_domain_desc a9_pwrc_domains[] = {
+	SEC_PD(A9_DSPA,		0),
+	SEC_PD(A9_U3HSG_U3,	0),
+	SEC_PD(A9_DP,		0),
+	SEC_PD(A9_DOS_HCODEC,	0),
+	SEC_PD(A9_TAHOE,	0),
+	SEC_PD(A9_DOS_HEVC,	0),
+	SEC_PD(A9_U2H,		0),
+	SEC_PD(A9_U3DRD_B,	0),
+	SEC_PD(A9_VPU_HDMI,	0),
+	SEC_PD(A9_U2DRD,	0),
+	SEC_PD(A9_U3DRD_A,	0),
+	SEC_PD(A9_SD_EMMC_C,	0),
+	SEC_PD(A9_GE2D,		0),
+	SEC_PD(A9_AMFC,		0),
+	SEC_PD(A9_EDPTX,	0),
+	SEC_PD(A9_OPP,		0),
+	SEC_PD(A9_VICP,		0),
+	SEC_PD(A9_SD_EMMC_A,	0),
+	SEC_PD(A9_SD_EMMC_B,	0),
+	SEC_PD(A9_ETH,		0),
+	SEC_PD(A9_PCIE_A,	0),
+	SEC_PD(A9_PCIE_B,	0),
+	SEC_PD(A9_NNA_4T,	0),
+	SEC_PD(A9_HDMIRX,	0),
+	SEC_PD(A9_CVE,		0),
+	SEC_PD(A9_ISP,		0),
+	SEC_PD(A9_ETH_1G,	0),
+	SEC_PD(A9_U3HSG_HSG,	0),
+	SEC_PD(A9_U3DPPHY_U3,	0),
+	SEC_PD(A9_U3DPPHY_DP,	0),
+	SEC_PD(A9_PCIE3PHY,	0),
+	SEC_PD(A9_U3HSG_PCIE2,	0),
+	SEC_PD(A9_MALI_TOP,	0),
+	SEC_PD(A9_AO_SED,	0),
+	SEC_PD(A9_AO_IR,	0),
+	/* UART_B is for console log, and should be always on */
+	SEC_PD(A9_AO_UART_B,	GENPD_FLAG_ALWAYS_ON),
+	SEC_PD(A9_AO_UART_C,	0),
+	SEC_PD(A9_AO_UART_D,	0),
+	SEC_PD(A9_AO_SPISG,	0),
+	SEC_PD(A9_AO_UART_E,	0),
+	SEC_PD(A9_AO_CEC,	0),
+	/* SRAMA is used as ATF runtime memory, and should be always on */
+	SEC_PD(A9_EE_SRAMA,	GENPD_FLAG_ALWAYS_ON),
+	SEC_PD(A9_AUDIO,	0),
+	/* DMC0 is for DDR PHY ana/dig and DMC, and should be always on */
+	SEC_PD(A9_DMC0,		GENPD_FLAG_ALWAYS_ON),
+	/*GIC needs to be used consistently, and should be always on */
+	SEC_PD(A9_GIC,		GENPD_FLAG_ALWAYS_ON),
+	/* DDRPHY is for DDR Work, and should be always on */
+	SEC_PD(A9_DDRPHY,	GENPD_FLAG_ALWAYS_ON),
+	SEC_PD(A9_AUCPU,	0),
+	SEC_PD(A9_DSI0,		0),
+	SEC_PD(A9_DSI1,		0),
+	SEC_PD(A9_CAN0,		0),
+	SEC_PD(A9_CAN1,		0),
+};
+
 static const struct meson_secure_pwrc_domain_desc c3_pwrc_domains[] = {
 	SEC_PD(C3_NNA,		0),
 	SEC_PD(C3_AUDIO,	0),
@@ -425,6 +485,11 @@ static const struct meson_secure_pwrc_domain_data amlogic_secure_a5_pwrc_data =
 	.count = ARRAY_SIZE(a5_pwrc_domains),
 };
 
+static const struct meson_secure_pwrc_domain_data amlogic_secure_a9_pwrc_data = {
+	.domains = a9_pwrc_domains,
+	.count = ARRAY_SIZE(a9_pwrc_domains),
+};
+
 static const struct meson_secure_pwrc_domain_data amlogic_secure_c3_pwrc_data = {
 	.domains = c3_pwrc_domains,
 	.count = ARRAY_SIZE(c3_pwrc_domains),
@@ -468,6 +533,10 @@ static const struct of_device_id meson_secure_pwrc_match_table[] = {
 		.compatible = "amlogic,a5-pwrc",
 		.data = &amlogic_secure_a5_pwrc_data,
 	},
+	{
+		.compatible = "amlogic,a9-pwrc",
+		.data = &amlogic_secure_a9_pwrc_data,
+	},
 	{
 		.compatible = "amlogic,c3-pwrc",
 		.data = &amlogic_secure_c3_pwrc_data,

-- 
2.52.0

[PATCH 3/3] arm64: dts: amlogic: a9: Add power domain controller node

[Xianwei Zhao via B4 Relay]

From: Xianwei Zhao <xianwei.zhao@amlogic.com>

Add power domain controller node for Amlogic A9 SoC.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi
index b0e0fadeed82..3652b2034c96 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
+#include <dt-bindings/power/amlogic,a9-pwrc.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -72,6 +73,15 @@ cpu7: cpu@700 {
 		};
 	};
 
+	sm: secure-monitor {
+		compatible = "amlogic,meson-gxbb-sm";
+
+		pwrc: power-controller {
+			compatible = "amlogic,a9-pwrc";
+			#power-domain-cells = <1>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

-- 
2.52.0

Re: [PATCH 2/3] pmdomain: amlogic: Add support for A9 power domains controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Use-After-Free due to missing .remove callback for meson_secure_pwrc driver
--

--- Patch [2]: [PATCH 2/3] pmdomain: amlogic: Add support for A9 power domains controller ---
commit 0074a5ab9b85f84325bfc2bf14c8fb48fcd14fb0
Author: Xianwei Zhao <xianwei.zhao@amlogic.com>

pmdomain: amlogic: Add support for A9 power domains controller

This commit adds support for the A9 power controller in the Amlogic
secure power domain driver. It introduces the A9 domain descriptors
and adds the corresponding compatible string to the match table.

> diff --git a/drivers/pmdomain/amlogic/meson-secure-pwrc.c b/drivers/pmdomain/amlogic/meson-secure-pwrc.c
> index 1d2f371d2d7f0..133549956efa4 100644
> --- a/drivers/pmdomain/amlogic/meson-secure-pwrc.c
> +++ b/drivers/pmdomain/amlogic/meson-secure-pwrc.c

[ ... ]

> @@ -468,6 +533,10 @@ static const struct of_device_id meson_secure_pwrc_match_table[] = {
>  		.compatible = "amlogic,a5-pwrc",
>  		.data = &amlogic_secure_a5_pwrc_data,
>  	},
> +	{
> +		.compatible = "amlogic,a9-pwrc",
> +		.data = &amlogic_secure_a9_pwrc_data,
> +	},
>  	{
>  		.compatible = "amlogic,c3-pwrc",
>  		.data = &amlogic_secure_c3_pwrc_data,
>  	},

[Severity: High]
This isn't a bug introduced by this patch, but while reviewing these
changes I noticed a pre-existing issue with the platform driver registration:

static struct platform_driver meson_secure_pwrc_driver = {
        .probe = meson_secure_pwrc_probe,
        .driver = {
                .name           = "meson_secure_pwrc",
                .of_match_table = meson_secure_pwrc_match_table,
        },
};

Does meson_secure_pwrc_driver lack a .remove callback?

If this driver is unbound via sysfs or unloaded as a module, it seems 
pm_genpd_remove(), pm_genpd_remove_subdomain(), and of_genpd_del_provider() 
are never called to deregister the domains.

Since the driver core's devres cleanup will free the memory allocated for 
the generic power domains upon removal, couldn't this leave dangling pointers 
in the global gpd_list and of_genpd_providers lists, causing a Use-After-Free 
when the power domain framework traverses them?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260722-a9-pm-v1-0-1fe20a44bf2d@amlogic.com?part=2