Re: [PATCH 3/6] ARM: dts: stm32: Use DMA FIFO mode for all spi in stm32mp151

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The SPI driver uses register accessors (`writel_relaxed`/`readl_relaxed`) instead of stream accessors for FIFO data buffers, causing inconsistent byte ordering between PIO and DMA transfers on big-endian systems.
--

--- Patch [3]: [PATCH 3/6] ARM: dts: stm32: Use DMA FIFO mode for all spi in stm32mp151 ---
commit d73fb38e89c8770514f3125ef0d74a5af311d84e
Author: Alain Volmat <alain.volmat@foss.st.com>

ARM: dts: stm32: Use DMA FIFO mode for all spi in stm32mp151

When used, configure the DMA in FIFO mode (instead of Direct) for all
SPI instances of stm32mp151.dtsi

> diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
> index 84f68e8563d85..e7fec8b49ae16 100644
> --- a/arch/arm/boot/dts/st/stm32mp151.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
[ ... ]
> @@ -943,8 +943,8 @@ spi2: spi@4000b000 {
>  				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>  				clocks = <&rcc SPI2_K>;
>  				resets = <&rcc SPI2_R>;
> -				dmas = <&dmamux1 39 0x400 0x05>,
> -				       <&dmamux1 40 0x400 0x05>;
> +				dmas = <&dmamux1 39 0x400 0x01>,
> +				       <&dmamux1 40 0x400 0x01>;

[Severity: High]
This is a pre-existing issue, but this change to use DMA FIFO mode highlights
a potential inconsistency in the SPI driver. Does this driver produce
inconsistent byte ordering between PIO and DMA transfers on big-endian
systems?

Looking at stm32h7_spi_write_txfifo() and stm32h7_spi_read_rxfifo() in
drivers/spi/spi-stm32.c, register accessors are used for FIFO data buffers:

drivers/spi/spi-stm32.c:stm32h7_spi_write_txfifo() {
    ...
    writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
    ...
}

drivers/spi/spi-stm32.c:stm32h7_spi_read_rxfifo() {
    ...
    *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
    ...
}

Because writel_relaxed() and readl_relaxed() perform CPU-to-LE byte swapping
on big-endian CPUs, PIO transfers will output a reversed byte order compared
to DMA transfers, which transfer memory exactly as-is without byte swapping.
Should these use stream accessors like writesl() and readsl() instead to
preserve byte order for FIFO buffers?

>  				dma-names = "rx", "tx";
>  				access-controllers = <&etzpc 27>;
>  				status = "disabled";

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260722-spi_arm_stm32_dt-v1-0-6ef611523232@foss.st.com?part=3