[PATCH 0/6] ARM: dts: stm32: enabling of SPI DMA/MDMA chaining on stm32mp13/mp15

[PATCH 0/6] ARM: dts: stm32: enabling of SPI DMA/MDMA chaining on stm32mp13/mp15

[Alain Volmat]

This series provides updates in the stm32mp15xx and stm32mp13xx
device-tree nodes in order to enable the STM32 SPI DMA/MDMA chaining.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
---
Alain Volmat (2):
      ARM: dts: stm32: Use DMA FIFO mode for all spi in stm32mp151
      ARM: dts: stm32: Add disabled spi4 and spi5 in stm32mp15xx-dkx

Clément Le Goffic (3):
      ARM: dts: stm32: add sram[123] nodes on stm32mp131
      ARM: dts: stm32: add sram pool to spi4 for DMA-MDMA chaining on MP15 DK
      ARM: dts: stm32: add sram pool to spi5 for DMA-MDMA chaining on MP13 DK

Valentin Caron (1):
      ARM: dts: stm32: add pins for spi4 and spi5 in stm32mp15-pinctrl

 arch/arm/boot/dts/st/stm32mp131.dtsi        | 24 ++++++++++++++++++++
 arch/arm/boot/dts/st/stm32mp135f-dk.dts     | 12 ++++++++++
 arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 34 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/st/stm32mp151.dtsi        | 20 ++++++++---------
 arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi   | 26 ++++++++++++++++++++++
 5 files changed, 106 insertions(+), 10 deletions(-)
---
base-commit: fba4a31a7f3b6b29b01c83180f83e7ed4c398738
change-id: 20260721-spi_arm_stm32_dt-c650d8a3d462

Best regards,
--  
Alain Volmat <alain.volmat@foss.st.com>

[PATCH 1/6] ARM: dts: stm32: add sram[123] nodes on stm32mp131

[Alain Volmat]

From: Clément Le Goffic <clement.legoffic@foss.st.com>

Add SRAM nodes with "mmio-sram" compatible in STM32MP131 SoC device
tree.
Those nodes describe the SRAM memory area (SRAM1 16kB, SRAM2 8kB, SRAM3
8kB).

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp131.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index 83ae59b73dd09..5ae33b26e313f 100644
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@ -139,6 +139,30 @@ soc {
 		interrupt-parent = <&intc>;
 		ranges;
 
+		sram1: sram@30000000 {
+			compatible = "mmio-sram";
+			reg = <0x30000000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x30000000 0x4000>;
+		};
+
+		sram2: sram@30004000 {
+			compatible = "mmio-sram";
+			reg = <0x30004000 0x2000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x30004000 0x2000>;
+		};
+
+		sram3: sram@30006000 {
+			compatible = "mmio-sram";
+			reg = <0x30006000 0x2000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x30006000 0x2000>;
+		};
+
 		timers2: timer@40000000 {
 			#address-cells = <1>;
 			#size-cells = <0>;

-- 
2.34.1

[PATCH 2/6] ARM: dts: stm32: add pins for spi4 and spi5 in stm32mp15-pinctrl

[Alain Volmat]

From: Valentin Caron <valentin.caron@foss.st.com>

Add pins for spi4 and spi5 in stm32mp15-pinctrl.dtsi

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 34 +++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi
index aaa91b634c12f..4480bc5292702 100644
--- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi
@@ -2873,6 +2873,31 @@ pins2 {
 		};
 	};
 
+	/omit-if-no-ref/
+	spi4_pins_b: spi4-1 {
+		pins1 {
+			pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
+				 <STM32_PINMUX('E', 14, AF5)>; /* SPI4_MOSI */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <1>;
+		};
+
+		pins2 {
+			pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
+			bias-disable;
+		};
+	};
+
+	/omit-if-no-ref/
+	spi4_sleep_pins_b: spi4-sleep-1 {
+		pins {
+			pinmux = <STM32_PINMUX('E', 12, ANALOG)>, /* SPI4_SCK */
+				 <STM32_PINMUX('E', 13, ANALOG)>, /* SPI4_MISO */
+				 <STM32_PINMUX('E', 14, ANALOG)>; /* SPI4_MOSI */
+		};
+	};
+
 	/omit-if-no-ref/
 	spi5_pins_a: spi5-0 {
 		pins1 {
@@ -2889,6 +2914,15 @@ pins2 {
 		};
 	};
 
+	/omit-if-no-ref/
+	spi5_sleep_pins_a: spi5-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* SPI5_SCK */
+				 <STM32_PINMUX('F', 8, ANALOG)>, /* SPI5_MISO */
+				 <STM32_PINMUX('F', 9, ANALOG)>; /* SPI5_MOSI */
+		};
+	};
+
 	/omit-if-no-ref/
 	stusb1600_pins_a: stusb1600-0 {
 		pins {

-- 
2.34.1

[PATCH 3/6] ARM: dts: stm32: Use DMA FIFO mode for all spi in stm32mp151

[Alain Volmat]

When used, configure the DMA in FIFO mode (instead of Direct) for all
SPI instances of stm32mp151.dtsi

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp151.dtsi | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
index 84f68e8563d85..e7fec8b49ae16 100644
--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
@@ -943,8 +943,8 @@ spi2: spi@4000b000 {
 				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&rcc SPI2_K>;
 				resets = <&rcc SPI2_R>;
-				dmas = <&dmamux1 39 0x400 0x05>,
-				       <&dmamux1 40 0x400 0x05>;
+				dmas = <&dmamux1 39 0x400 0x01>,
+				       <&dmamux1 40 0x400 0x01>;
 				dma-names = "rx", "tx";
 				access-controllers = <&etzpc 27>;
 				status = "disabled";
@@ -970,8 +970,8 @@ spi3: spi@4000c000 {
 				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&rcc SPI3_K>;
 				resets = <&rcc SPI3_R>;
-				dmas = <&dmamux1 61 0x400 0x05>,
-				       <&dmamux1 62 0x400 0x05>;
+				dmas = <&dmamux1 61 0x400 0x01>,
+				       <&dmamux1 62 0x400 0x01>;
 				dma-names = "rx", "tx";
 				access-controllers = <&etzpc 28>;
 				status = "disabled";
@@ -1301,8 +1301,8 @@ spi1: spi@44004000 {
 				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&rcc SPI1_K>;
 				resets = <&rcc SPI1_R>;
-				dmas = <&dmamux1 37 0x400 0x05>,
-				       <&dmamux1 38 0x400 0x05>;
+				dmas = <&dmamux1 37 0x400 0x01>,
+				       <&dmamux1 38 0x400 0x01>;
 				dma-names = "rx", "tx";
 				access-controllers = <&etzpc 52>;
 				status = "disabled";
@@ -1316,8 +1316,8 @@ spi4: spi@44005000 {
 				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&rcc SPI4_K>;
 				resets = <&rcc SPI4_R>;
-				dmas = <&dmamux1 83 0x400 0x05>,
-				       <&dmamux1 84 0x400 0x05>;
+				dmas = <&dmamux1 83 0x400 0x01>,
+				       <&dmamux1 84 0x400 0x01>;
 				dma-names = "rx", "tx";
 				access-controllers = <&etzpc 53>;
 				status = "disabled";
@@ -1432,8 +1432,8 @@ spi5: spi@44009000 {
 				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&rcc SPI5_K>;
 				resets = <&rcc SPI5_R>;
-				dmas = <&dmamux1 85 0x400 0x05>,
-				       <&dmamux1 86 0x400 0x05>;
+				dmas = <&dmamux1 85 0x400 0x01>,
+				       <&dmamux1 86 0x400 0x01>;
 				dma-names = "rx", "tx";
 				access-controllers = <&etzpc 57>;
 				status = "disabled";

-- 
2.34.1

[PATCH 4/6] ARM: dts: stm32: Add disabled spi4 and spi5 in stm32mp15xx-dkx

[Alain Volmat]

Add disabled spi4 and spi5 nodes within stm32mp15xx-dkx.

SPI4 can be accessed via the Arduino connectors
SPI5 can be accessed via the GPIO expansion connectors.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
index 599ea07bdb19c..681e9b1106025 100644
--- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
@@ -623,6 +623,20 @@ &sdmmc3 {
 	status = "disabled";
 };
 
+&spi4 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&spi4_pins_b>;
+	pinctrl-1 = <&spi4_sleep_pins_b>;
+	status = "disabled";
+};
+
+&spi5 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&spi5_pins_a>;
+	pinctrl-1 = <&spi5_sleep_pins_a>;
+	status = "disabled";
+};
+
 &timers1 {
 	/* spare dmas for other usage */
 	/delete-property/dmas;

-- 
2.34.1

[PATCH 5/6] ARM: dts: stm32: add sram pool to spi4 for DMA-MDMA chaining on MP15 DK

[Alain Volmat]

From: Clément Le Goffic <clement.legoffic@foss.st.com>

The sram pool is used as a buffer area during a spi transfer using
DMA-MDMA chaining.
The pool size depends on the SPI framework that creates sg up to
4096 bytes.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
index 681e9b1106025..580f7da7f63f2 100644
--- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
@@ -627,6 +627,11 @@ &spi4 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&spi4_pins_b>;
 	pinctrl-1 = <&spi4_sleep_pins_b>;
+	dmas = <&dmamux1 83 0x400 0x01>,
+	       <&dmamux1 84 0x400 0x01>,
+	       <&mdma1 0 0x3 0x1200000a 0 0>;
+	dma-names = "rx", "tx", "rxm2m";
+	sram = <&spi4_dma_pool>;
 	status = "disabled";
 };
 
@@ -637,6 +642,13 @@ &spi5 {
 	status = "disabled";
 };
 
+&sram4 {
+	spi4_dma_pool: dma-sram@9000 {
+		reg = <0x9000 0x1000>;
+		pool;
+	};
+};
+
 &timers1 {
 	/* spare dmas for other usage */
 	/delete-property/dmas;

-- 
2.34.1

[PATCH 6/6] ARM: dts: stm32: add sram pool to spi5 for DMA-MDMA chaining on MP13 DK

[Alain Volmat]

From: Clément Le Goffic <clement.legoffic@foss.st.com>

The sram pool is used as a buffer area during a spi transfer using
DMA-MDMA chaining.
The pool size depends on the SPI framework that creates sg up to
4096 bytes.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp135f-dk.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index 6022e73f58afd..35509b5c3872a 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -479,9 +479,21 @@ &spi5 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&spi5_pins_a>;
 	pinctrl-1 = <&spi5_sleep_pins_a>;
+	dmas = <&dmamux1 85 0x400 0x01>,
+	       <&dmamux1 86 0x400 0x01>,
+	       <&mdma 0 0x3 0x1200000a 0 0>;
+	dma-names = "rx", "tx", "rxm2m";
+	sram = <&spi5_dma_pool>;
 	status = "disabled";
 };
 
+&sram2 {
+	spi5_dma_pool: dma-sram@1000 {
+		reg = <0x1000 0x1000>;
+		pool;
+	};
+};
+
 &timers3 {
 	/delete-property/dmas;
 	/delete-property/dma-names;

-- 
2.34.1

Re: [PATCH 3/6] ARM: dts: stm32: Use DMA FIFO mode for all spi in stm32mp151

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The SPI driver uses register accessors (`writel_relaxed`/`readl_relaxed`) instead of stream accessors for FIFO data buffers, causing inconsistent byte ordering between PIO and DMA transfers on big-endian systems.
--

--- Patch [3]: [PATCH 3/6] ARM: dts: stm32: Use DMA FIFO mode for all spi in stm32mp151 ---
commit d73fb38e89c8770514f3125ef0d74a5af311d84e
Author: Alain Volmat <alain.volmat@foss.st.com>

ARM: dts: stm32: Use DMA FIFO mode for all spi in stm32mp151

When used, configure the DMA in FIFO mode (instead of Direct) for all
SPI instances of stm32mp151.dtsi

> diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
> index 84f68e8563d85..e7fec8b49ae16 100644
> --- a/arch/arm/boot/dts/st/stm32mp151.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
[ ... ]
> @@ -943,8 +943,8 @@ spi2: spi@4000b000 {
>  				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>  				clocks = <&rcc SPI2_K>;
>  				resets = <&rcc SPI2_R>;
> -				dmas = <&dmamux1 39 0x400 0x05>,
> -				       <&dmamux1 40 0x400 0x05>;
> +				dmas = <&dmamux1 39 0x400 0x01>,
> +				       <&dmamux1 40 0x400 0x01>;

[Severity: High]
This is a pre-existing issue, but this change to use DMA FIFO mode highlights
a potential inconsistency in the SPI driver. Does this driver produce
inconsistent byte ordering between PIO and DMA transfers on big-endian
systems?

Looking at stm32h7_spi_write_txfifo() and stm32h7_spi_read_rxfifo() in
drivers/spi/spi-stm32.c, register accessors are used for FIFO data buffers:

drivers/spi/spi-stm32.c:stm32h7_spi_write_txfifo() {
    ...
    writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
    ...
}

drivers/spi/spi-stm32.c:stm32h7_spi_read_rxfifo() {
    ...
    *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
    ...
}

Because writel_relaxed() and readl_relaxed() perform CPU-to-LE byte swapping
on big-endian CPUs, PIO transfers will output a reversed byte order compared
to DMA transfers, which transfer memory exactly as-is without byte swapping.
Should these use stream accessors like writesl() and readsl() instead to
preserve byte order for FIFO buffers?

>  				dma-names = "rx", "tx";
>  				access-controllers = <&etzpc 27>;
>  				status = "disabled";

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260722-spi_arm_stm32_dt-v1-0-6ef611523232@foss.st.com?part=3