* [PATCH v19 2/4] arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK
2026-07-23 15:41 [PATCH v19 0/4] Add SDHI support for RZ/G3L SoC Biju
@ 2026-07-23 15:41 ` Biju
2026-07-23 16:03 ` sashiko-bot
2026-07-23 15:41 ` [PATCH v19 3/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0 Biju
2026-07-23 15:41 ` [PATCH v19 4/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SDHI2 Biju
2 siblings, 1 reply; 6+ messages in thread
From: Biju @ 2026-07-23 15:41 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add device tree nodes for the three SDHI controllers (SDHI{0,1,2})
on the RZ/G3L SoC (r9a08g046) and enable SDHI1 on the RZ/G3L SMARC
EVK platform with pincontrol and GPIO-based voltage switching
regulator support.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v18->v19:
* Renamed aclk->aclks as it is AXI bus slave clock.
* Rearranged AXI bus master and slave clocks as per binding.
v17->v18:
* No change.
* This patch depend on [1]
[1] https://lore.kernel.org/all/20260622155610.184271-2-biju.das.jz@bp.renesas.com/
v1->v17:
* No change.
---
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 73 ++++++++++++++-
.../boot/dts/renesas/r9a08g046l48-smarc.dts | 88 +++++++++++++++++++
2 files changed, 160 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index c63a857f0e5b..3665ccbdd91b 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -762,9 +762,80 @@ dmac: dma-controller@11820000 {
dma-channels = <16>;
};
+ sdhi0: mmc@11c00000 {
+ compatible = "renesas,sdhi-r9a08g046";
+ reg = <0x0 0x11c00000 0 0x10000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_SDHI0_IMCLK>,
+ <&cpg CPG_MOD R9A08G046_SDHI0_CLK_HS>,
+ <&cpg CPG_MOD R9A08G046_SDHI0_IMCLK2>,
+ <&cpg CPG_MOD R9A08G046_SDHI0_IACLKM>,
+ <&cpg CPG_MOD R9A08G046_SDHI0_IACLKS>;
+ clock-names = "core", "clkh", "cd", "aclkm", "aclks";
+ max-frequency = <150000000>;
+ resets = <&cpg R9A08G046_SDHI0_IXRST>,
+ <&cpg R9A08G046_SDHI0_IXRSTAXIM>,
+ <&cpg R9A08G046_SDHI0_IXRSTAXIS>;
+ reset-names = "rst", "axim", "axis";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
sdhi1: mmc@11c10000 {
+ compatible = "renesas,sdhi-r9a08g046";
reg = <0x0 0x11c10000 0 0x10000>;
- /* placeholder */
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_SDHI1_IMCLK>,
+ <&cpg CPG_MOD R9A08G046_SDHI1_CLK_HS>,
+ <&cpg CPG_MOD R9A08G046_SDHI1_IMCLK2>,
+ <&cpg CPG_MOD R9A08G046_SDHI1_IACLKM>,
+ <&cpg CPG_MOD R9A08G046_SDHI1_IACLKS>;
+ clock-names = "core", "clkh", "cd", "aclkm", "aclks";
+ max-frequency = <150000000>;
+ resets = <&cpg R9A08G046_SDHI1_IXRST>,
+ <&cpg R9A08G046_SDHI1_IXRSTAXIM>,
+ <&cpg R9A08G046_SDHI1_IXRSTAXIS>;
+ reset-names = "rst", "axim", "axis";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi1_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI1-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <1200>;
+ status = "disabled";
+ };
+ };
+
+ sdhi2: mmc@11c20000 {
+ compatible = "renesas,sdhi-r9a08g046";
+ reg = <0x0 0x11c20000 0 0x10000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_SDHI2_IMCLK>,
+ <&cpg CPG_MOD R9A08G046_SDHI2_CLK_HS>,
+ <&cpg CPG_MOD R9A08G046_SDHI2_IMCLK2>,
+ <&cpg CPG_MOD R9A08G046_SDHI2_IACLKM>,
+ <&cpg CPG_MOD R9A08G046_SDHI2_IACLKS>;
+ clock-names = "core", "clkh", "cd", "aclkm", "aclks";
+ max-frequency = <150000000>;
+ resets = <&cpg R9A08G046_SDHI2_IXRST>,
+ <&cpg R9A08G046_SDHI2_IXRSTAXIM>,
+ <&cpg R9A08G046_SDHI2_IXRSTAXIS>;
+ reset-names = "rst", "axim", "axis";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi2_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI2-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <1200>;
+ status = "disabled";
+ };
};
eth0: ethernet@11c30000 {
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
index 5289efd1a430..0b6b7e109200 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
@@ -14,6 +14,7 @@
#define SW_GPIO4 1
#define SW_I3C_EN 0
#define SW_SER0_PMOD 1
+#define SW_SDIO_M2E 0
#define PMOD_GPIO4 0
#define PMOD_GPIO6 0
@@ -38,6 +39,7 @@ / {
aliases {
i2c2 = &i2c2;
i2c3 = &i2c3;
+ mmc1 = &sdhi1;
serial0 = &rsci2;
serial1 = &rsci3;
serial2 = &rsci1;
@@ -69,6 +71,19 @@ codec_dai: codec {
};
};
#endif
+
+#if RZ_BOOT_MODE3
+ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
+ compatible = "regulator-gpio";
+ regulator-name = "SD1_PVDD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pinctrl RZG3L_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <3300000 0>, <1800000 1>;
+ regulator-ramp-delay = <1200>;
+ };
+#endif
};
&i2c2 {
@@ -175,6 +190,68 @@ scif0_pins: scif0 {
power-source = <1800>;
};
+#if RZ_BOOT_MODE3
+ sd1-pwr-en-hog {
+ gpio-hog;
+ gpios = <RZG3L_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "sd1_pwr_en";
+ };
+#endif
+
+ sdhi1_pins: sd1 {
+ sd1-cd {
+ pinmux = <RZG3L_PORT_PINMUX(J, 0, 8)>; /* SD1_CD */
+ };
+
+ sd1-clk {
+ pinmux = <RZG3L_PORT_PINMUX(G, 0, 1)>; /* SD1_CLK */
+ power-source = <3300>;
+ };
+
+ sd1-cmd {
+ pinmux = <RZG3L_PORT_PINMUX(G, 1, 1)>; /* SD1_CMD */
+ input-enable;
+ power-source = <3300>;
+ bias-pull-up;
+ };
+
+ sd1-data {
+ pinmux = <RZG3L_PORT_PINMUX(G, 2, 1)>, /* SD1_DAT0 */
+ <RZG3L_PORT_PINMUX(G, 3, 1)>, /* SD1_DAT1 */
+ <RZG3L_PORT_PINMUX(G, 4, 1)>, /* SD1_DAT2 */
+ <RZG3L_PORT_PINMUX(G, 5, 1)>; /* SD1_DAT3 */
+ input-enable;
+ power-source = <3300>;
+ };
+ };
+
+ sdhi1_uhs_pins: sd1-uhs {
+ sd1-cd {
+ pinmux = <RZG3L_PORT_PINMUX(J, 0, 8)>; /* SD1_CD */
+ };
+
+ sd1-clk {
+ pinmux = <RZG3L_PORT_PINMUX(G, 0, 1)>; /* SD1_CLK */
+ power-source = <1800>;
+ };
+
+ sd1-cmd {
+ pinmux = <RZG3L_PORT_PINMUX(G, 1, 1)>; /* SD1_CMD */
+ input-enable;
+ power-source = <1800>;
+ };
+
+ sd1-data {
+ pinmux = <RZG3L_PORT_PINMUX(G, 2, 1)>, /* SD1_DAT0 */
+ <RZG3L_PORT_PINMUX(G, 3, 1)>, /* SD1_DAT1 */
+ <RZG3L_PORT_PINMUX(G, 4, 1)>, /* SD1_DAT2 */
+ <RZG3L_PORT_PINMUX(G, 5, 1)>; /* SD1_DAT3 */
+ input-enable;
+ power-source = <1800>;
+ };
+ };
+
ssi0_pins: ssi0 {
pinmux = <RZG3L_PORT_PINMUX(H, 0, 9)>, /* SSIF0_RXD */
<RZG3L_PORT_PINMUX(H, 1, 9)>, /* SSIF0_BCK */
@@ -230,6 +307,17 @@ &scif0 {
pinctrl-names = "default";
};
+#if RZ_BOOT_MODE3
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_uhs_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <&vqmmc_sd1_pvdd>;
+};
+#endif
+
#if !SW_SD2_EN
&ssi0 {
clocks = <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>,
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v19 2/4] arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK
2026-07-23 15:41 ` [PATCH v19 2/4] arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK Biju
@ 2026-07-23 16:03 ` sashiko-bot
0 siblings, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-07-23 16:03 UTC (permalink / raw)
To: Biju; +Cc: wsa+renesas, robh, devicetree, conor+dt
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The SDHI device tree nodes specify only the SoC-specific compatible string (`renesas,sdhi-r9a08g046`) and omit the required fallback string (`renesas,rzg2l-sdhi`).
- [Medium] Missing `#else` branch leaves `sdhi1` enabled without pin multiplexing or supplies when `RZ_BOOT_MODE3` is disabled.
- [Medium] The pin configuration for `sd1-data` in the `sdhi1_pins` and `sdhi1_uhs_pins` nodes is missing the `bias-pull-up` property.
--
--- Patch [2]: [PATCH v19 2/4] arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK ---
commit 6289153083cb6f174266f6b60614c70a75cd4294
Author: Biju Das <biju.das.jz@bp.renesas.com>
arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK
Add device tree nodes for the three SDHI controllers (SDHI{0,1,2})
on the RZ/G3L SoC (r9a08g046) and enable SDHI1 on the RZ/G3L SMARC
EVK platform with pincontrol and GPIO-based voltage switching
regulator support.
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -762,9 +762,80 @@ dmac: dma-controller@11820000 {
> dma-channels = <16>;
> };
>
> + sdhi0: mmc@11c00000 {
> + compatible = "renesas,sdhi-r9a08g046";
[Severity: High]
Does this node need the "renesas,rzg2l-sdhi" fallback compatible string?
The driver source code for SDHI does not contain a direct match for
"renesas,sdhi-r9a08g046", so it relies on the "renesas,rzg2l-sdhi"
fallback to successfully probe the device. Without the fallback string,
the driver will not probe the controllers, breaking SD/eMMC support.
This same issue also appears in the sdhi1 and sdhi2 nodes below.
[ ... ]
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
> --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
[ ... ]
> + sdhi1_pins: sd1 {
> + sd1-cd {
> + pinmux = <RZG3L_PORT_PINMUX(J, 0, 8)>; /* SD1_CD */
> + };
> +
> + sd1-clk {
> + pinmux = <RZG3L_PORT_PINMUX(G, 0, 1)>; /* SD1_CLK */
> + power-source = <3300>;
> + };
> +
> + sd1-cmd {
> + pinmux = <RZG3L_PORT_PINMUX(G, 1, 1)>; /* SD1_CMD */
> + input-enable;
> + power-source = <3300>;
> + bias-pull-up;
> + };
> +
> + sd1-data {
> + pinmux = <RZG3L_PORT_PINMUX(G, 2, 1)>, /* SD1_DAT0 */
> + <RZG3L_PORT_PINMUX(G, 3, 1)>, /* SD1_DAT1 */
> + <RZG3L_PORT_PINMUX(G, 4, 1)>, /* SD1_DAT2 */
> + <RZG3L_PORT_PINMUX(G, 5, 1)>; /* SD1_DAT3 */
> + input-enable;
> + power-source = <3300>;
[Severity: Medium]
Should the data lines also specify bias-pull-up?
The sd1-cmd node correctly includes bias-pull-up. If the board relies on
the SoC's internal pull-ups rather than external resistors, leaving the data
lines floating when the bus is idle could lead to intermittent SD card
communication errors.
This also applies to the sdhi1_uhs_pins configuration.
[ ... ]
> +#if RZ_BOOT_MODE3
> +&sdhi1 {
> + pinctrl-0 = <&sdhi1_pins>;
> + pinctrl-1 = <&sdhi1_uhs_pins>;
> + pinctrl-names = "default", "state_uhs";
> +
> + vmmc-supply = <®_3p3v>;
> + vqmmc-supply = <&vqmmc_sd1_pvdd>;
> +};
> +#endif
[Severity: Medium]
Does this conditional block need an #else branch to set status = "disabled"
for &sdhi1 when RZ_BOOT_MODE3 is false?
Since the included renesas-smarc2.dtsi unconditionally sets status = "okay"
for &sdhi1, failing to disable it here when RZ_BOOT_MODE3 is 0 leaves the
node enabled but without required pin multiplexing and supplies. The MMC driver
would then attempt to probe a non-routed device, which could lead to timeouts
and boot delays.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260723154154.319674-1-biju.das.jz@bp.renesas.com?part=2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v19 3/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0
2026-07-23 15:41 [PATCH v19 0/4] Add SDHI support for RZ/G3L SoC Biju
2026-07-23 15:41 ` [PATCH v19 2/4] arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK Biju
@ 2026-07-23 15:41 ` Biju
2026-07-23 15:55 ` sashiko-bot
2026-07-23 15:41 ` [PATCH v19 4/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SDHI2 Biju
2 siblings, 1 reply; 6+ messages in thread
From: Biju @ 2026-07-23 15:41 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add support for enabling SD card or eMMC on SDHI0 on the RZ/G3L SMARC
SoM. The selection between SD and eMMC is controlled by the
SW_SD0_DEV_SEL macro in the board DTS, which must match the position
of switch SYS.1 on the SoM. By default, eMMC is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v18->v19:
* Split SD0_CLK and SD0_CMD separate as input enable not available for
SD0_CLK.
* Added bias_pull_down, input enable, default drive strength for SD0_DS.
* Added input enable for SD0_CMD and SD0_DAT*
* Added default drive-strength for all SD0 pins except cd.
v17->v18:
* No change.
v1->v17:
* No change.
---
.../boot/dts/renesas/r9a08g046l48-smarc.dts | 1 +
.../boot/dts/renesas/rzg3l-smarc-som.dtsi | 145 ++++++++++++++++++
2 files changed, 146 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
index 0b6b7e109200..96cc7ee46a6a 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
@@ -9,6 +9,7 @@
/* Switch selection settings */
#define RZ_BOOT_MODE3 1
+#define SW_SD0_DEV_SEL 0
#define SW_SD2_EN 0
#define SW_DPI_EN 0
#define SW_GPIO4 1
diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
index 091a227233cb..c365b8087520 100644
--- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
@@ -9,6 +9,10 @@
* Please set the below switch position on the SoM and the corresponding macro
* on the board DTS:
*
+ * Switch position SYS.1, Macro SW_SD0_DEV_SEL:
+ * 0 - SD0 is connected to eMMC (default)
+ * 1 - SD0 is connected to uSD0 card
+ *
* Switch position SYS.2, Macro SW_I3C_EN:
* 0 - SMARC_I2C_GP is enabled
* 1 - I3C is enabled
@@ -37,6 +41,7 @@ aliases {
ethernet0 = ð0;
ethernet1 = ð1;
i2c0 = &i2c0;
+ mmc0 = &sdhi0;
};
memory@48000000 {
@@ -63,6 +68,19 @@ reg_3p3v: regulator-3p3v {
regulator-always-on;
};
+#if SW_SD0_DEV_SEL
+ vqmmc_sd0_pvdd: vqmmc-sd0-pvdd {
+ compatible = "regulator-gpio";
+ regulator-name = "SD0_PVDD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pinctrl RZG3L_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <3300000 0>, <1800000 1>;
+ regulator-ramp-delay = <1200>;
+ };
+#endif
+
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -216,7 +234,134 @@ i2c0_pins: i2c0 {
pinmux = <RZG3L_PORT_PINMUX(L, 2, 4)>, /* RIIC0_SCL */
<RZG3L_PORT_PINMUX(L, 3, 4)>; /* RIIC0_SDA */
};
+
+ sd0-pwr-en-hog {
+ gpio-hog;
+ gpios = <RZG3L_GPIO(5, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "sd0_pwr_en";
+ };
+
+ sdhi0_emmc_pins: sd0-emmc {
+ sd0-clk {
+ pins = "SD0_CLK";
+ power-source = <1800>;
+ drive-strength-microamp = <9000>;
+ };
+
+ sd0-cmd {
+ pins = "SD0_CMD";
+ input-enable;
+ drive-strength-microamp = <9000>;
+ power-source = <1800>;
+ };
+
+ sd0-data {
+ pins = "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3",
+ "SD0_DAT4", "SD0_DAT5", "SD0_DAT6", "SD0_DAT7";
+ input-enable;
+ drive-strength-microamp = <9000>;
+ power-source = <1800>;
+ };
+
+ sd0-rst {
+ pins = "SD0_RST#";
+ drive-strength-microamp = <9000>;
+ power-source = <1800>;
+ };
+
+ sd0-ds {
+ pins = "SD0_DS";
+ input-enable;
+ bias-pull-down;
+ drive-strength-microamp = <9000>;
+ power-source = <1800>;
+ };
+ };
+
+ sdhi0_usd_pins: sd0-usd {
+ sd0-cd {
+ pinmux = <RZG2L_PORT_PINMUX(5, 0, 8)>; /* SD0_CD */
+ };
+
+ sd0-clk {
+ pins = "SD0_CLK";
+ drive-strength-microamp = <8000>;
+ power-source = <3300>;
+ };
+
+ sd0-cmd {
+ pins = "SD0_CMD";
+ input-enable;
+ drive-strength-microamp = <8000>;
+ power-source = <3300>;
+ };
+
+ sd0-data {
+ pins = "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3";
+ input-enable;
+ drive-strength-microamp = <8000>;
+ power-source = <3300>;
+ };
+ };
+
+ sdhi0_usd_uhs_pins: sd0-usd-uhs {
+ sd0-cd {
+ pinmux = <RZG2L_PORT_PINMUX(5, 0, 8)>; /* SD0_CD */
+ };
+
+ sd0-clk {
+ pins = "SD0_CLK";
+ drive-strength-microamp = <9000>;
+ power-source = <1800>;
+ };
+
+ sd0-cmd {
+ pins = "SD0_CMD";
+ input-enable;
+ drive-strength-microamp = <9000>;
+ power-source = <1800>;
+ };
+
+ sd0-data {
+ pins = "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3";
+ input-enable;
+ drive-strength-microamp = <9000>;
+ power-source = <1800>;
+ };
+ };
+};
+
+#if (SW_SD0_DEV_SEL)
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_usd_pins>;
+ pinctrl-1 = <&sdhi0_usd_uhs_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <&vqmmc_sd0_pvdd>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+#else
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_emmc_pins>;
+ pinctrl-1 = <&sdhi0_emmc_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ fixed-emmc-driver-type = <1>;
+ status = "okay";
};
+#endif
&wdt0 {
timeout-sec = <60>;
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v19 3/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0
2026-07-23 15:41 ` [PATCH v19 3/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0 Biju
@ 2026-07-23 15:55 ` sashiko-bot
0 siblings, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-07-23 15:55 UTC (permalink / raw)
To: Biju; +Cc: robh, devicetree, conor+dt, wsa+renesas
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Inconsistent use of the RZG2L_PORT_PINMUX macro in a file that otherwise strictly uses RZG3L_PORT_PINMUX.
--
--- Patch [3]: [PATCH v19 3/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0 ---
commit dcc213ca53944f7a953171eac4a8625b70907250
Author: Biju Das <biju.das.jz@bp.renesas.com>
arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0
This commit adds support for enabling SD card or eMMC on SDHI0 on the
RZ/G3L SMARC SoM. The selection between SD and eMMC is controlled by the
SW_SD0_DEV_SEL macro in the board DTS. By default, eMMC is enabled.
> diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
> index 091a227233cba..c365b8087520b 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
[ ... ]
> @@ -216,7 +234,134 @@ i2c0_pins: i2c0 {
[ ... ]
> + sdhi0_usd_pins: sd0-usd {
> + sd0-cd {
> + pinmux = <RZG2L_PORT_PINMUX(5, 0, 8)>; /* SD0_CD */
[Severity: Low]
This isn't a bug, but should this macro be RZG3L_PORT_PINMUX(5, 0, 8) instead?
Since the rest of the file appears to use the RZG3L_PORT_PINMUX wrapper,
would it make sense to keep the styling consistent?
> + };
> +
> + sd0-clk {
[ ... ]
> + sdhi0_usd_uhs_pins: sd0-usd-uhs {
> + sd0-cd {
> + pinmux = <RZG2L_PORT_PINMUX(5, 0, 8)>; /* SD0_CD */
[Severity: Low]
This isn't a bug, but the same question applies here regarding the use of
RZG2L_PORT_PINMUX instead of the RZG3L variant.
> + };
> +
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260723154154.319674-1-biju.das.jz@bp.renesas.com?part=3
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v19 4/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SDHI2
2026-07-23 15:41 [PATCH v19 0/4] Add SDHI support for RZ/G3L SoC Biju
2026-07-23 15:41 ` [PATCH v19 2/4] arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK Biju
2026-07-23 15:41 ` [PATCH v19 3/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0 Biju
@ 2026-07-23 15:41 ` Biju
2 siblings, 0 replies; 6+ messages in thread
From: Biju @ 2026-07-23 15:41 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Enable SDHI2 on the RZ/G3L SMARC EVK platform using the internal
voltage regulator for voltage switching. SDHI2 signals are muxed
with I2S0; the selection is controlled by the SW_SD2_EN macro in
the board DTS, which must match the position of switch SYS.4 on
the SoM. By default, I2S0 is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v18->v19:
* No change.
v17->v18:
* No change.
v1->v17:
* No change.
---
.../boot/dts/renesas/rzg3l-smarc-som.dtsi | 88 +++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
index c365b8087520..1b72c310830e 100644
--- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
@@ -42,6 +42,7 @@ aliases {
ethernet1 = ð1;
i2c0 = &i2c0;
mmc0 = &sdhi0;
+ mmc2 = &sdhi2;
};
memory@48000000 {
@@ -330,6 +331,74 @@ sd0-data {
power-source = <1800>;
};
};
+
+ sdhi2_pins: sd2 {
+ sd2-cd {
+ pinmux = <RZG3L_PORT_PINMUX(K, 0, 1)>; /* SD2_CD */
+ };
+
+ sd2-clk {
+ pinmux = <RZG3L_PORT_PINMUX(H, 0, 1)>; /* SD2_CLK */
+ power-source = <3300>;
+ };
+
+ sd2-cmd {
+ pinmux = <RZG3L_PORT_PINMUX(H, 1, 1)>; /* SD2_CMD */
+ input-enable;
+ power-source = <3300>;
+ };
+
+ sd2-data {
+ pinmux = <RZG3L_PORT_PINMUX(H, 2, 1)>, /* SD2_DAT0 */
+ <RZG3L_PORT_PINMUX(H, 3, 1)>, /* SD2_DAT1 */
+ <RZG3L_PORT_PINMUX(H, 4, 1)>, /* SD2_DAT2 */
+ <RZG3L_PORT_PINMUX(H, 5, 1)>; /* SD2_DAT3 */
+ input-enable;
+ power-source = <3300>;
+ };
+
+ sd2-iovs {
+ pinmux = <RZG3L_PORT_PINMUX(K, 1, 1)>; /* SD2_IOVS */
+ };
+
+ sd2-pwen {
+ pinmux = <RZG3L_PORT_PINMUX(K, 2, 1)>; /* SD2_PWEN */
+ };
+ };
+
+ sdhi2_pins_uhs: sd2-uhs {
+ sd2-cd {
+ pinmux = <RZG3L_PORT_PINMUX(K, 0, 1)>; /* SD2_CD */
+ };
+
+ sd2-clk {
+ pinmux = <RZG3L_PORT_PINMUX(H, 0, 1)>; /* SD2_CLK */
+ power-source = <1800>;
+ };
+
+ sd2-cmd {
+ pinmux = <RZG3L_PORT_PINMUX(H, 1, 1)>; /* SD2_CMD */
+ input-enable;
+ power-source = <1800>;
+ };
+
+ sd2-data {
+ pinmux = <RZG3L_PORT_PINMUX(H, 2, 1)>, /* SD2_DAT0 */
+ <RZG3L_PORT_PINMUX(H, 3, 1)>, /* SD2_DAT1 */
+ <RZG3L_PORT_PINMUX(H, 4, 1)>, /* SD2_DAT2 */
+ <RZG3L_PORT_PINMUX(H, 5, 1)>; /* SD2_DAT3 */
+ input-enable;
+ power-source = <1800>;
+ };
+
+ sd2-iovs {
+ pinmux = <RZG3L_PORT_PINMUX(K, 1, 1)>; /* SD2_IOVS */
+ };
+
+ sd2-pwen {
+ pinmux = <RZG3L_PORT_PINMUX(K, 2, 1)>; /* SD2_PWEN */
+ };
+ };
};
#if (SW_SD0_DEV_SEL)
@@ -363,6 +432,25 @@ &sdhi0 {
};
#endif
+#if SW_SD2_EN
+&sdhi2 {
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <&sdhi2_vqmmc>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi2_vqmmc {
+ status = "okay";
+};
+#endif
+
&wdt0 {
timeout-sec = <60>;
status = "okay";
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread