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From: sashiko-bot@kernel.org
To: "Liu Changjie" <liucj1228@outlook.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH RESEND 7/9] ARM: dts: stm32: add STM32H7R7 SoC
Date: Sun, 26 Jul 2026 16:26:39 +0000	[thread overview]
Message-ID: <20260726162640.6442E1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <MN0PR19MB609159EC2888184313D616F8ACCD2@MN0PR19MB6091.namprd19.prod.outlook.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Mismatch between unit-address and `reg` property in GPIO bank nodes within the `pinctrl` block.
--

--- Patch [7]: [PATCH RESEND 7/9] ARM: dts: stm32: add STM32H7R7 SoC ---
commit e7124a5b13abf93e1321e7a33e469a82c2e13c42
Author: Liu Changjie <liucj1228@outlook.com>

ARM: dts: stm32: add STM32H7R7 SoC

This commit adds the device tree include file for the STM32H7R7 SoC. It
describes the CPU, clocks, timers, UART, SDMMC, and various GPIO banks within
the pinctrl block.

> diff --git a/arch/arm/boot/dts/st/stm32h7r7.dtsi b/arch/arm/boot/dts/st/stm32h7r7.dtsi
> new file mode 100644
> index 0000000000000..ad25dddbe6ed8
> --- /dev/null
> +++ b/arch/arm/boot/dts/st/stm32h7r7.dtsi

[ ... ]

> +		pinctrl: pinctrl@58020000 {
> +			compatible = "st,stm32h7rs-pinctrl";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0x58020000 0x4000>;
> +			interrupt-parent = <&exti>;
> +			st,syscfg = <&syscfg 0x130>;
> +
> +			gpioa: gpio@58020000 {
> +				reg = <0x0 0x400>;

[Severity: Low]
Should the unit-address match the first address specified in the reg
property? Because the parent pinctrl node sets ranges = <0 0x58020000 0x4000>,
the child nodes' reg properties are relative to 0. Would it be better to use
gpio@0 instead of gpio@58020000 to avoid dtc -Wunit_address_vs_reg warnings?

This pattern appears to repeat for the subsequent GPIO banks as well, such as
gpiob: gpio@58020400 having reg = <0x400 0x400>.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/MN0PR19MB60912FA1E75E4E55B2E27D34ACCD2@MN0PR19MB6091.namprd19.prod.outlook.com?part=7

  reply	other threads:[~2026-07-26 16:26 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-26 15:49 [PATCH RESEND 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie
2026-07-23 15:48 ` [PATCH RESEND 1/9] dt-bindings: arm: stm32: add Ruiside ART-Pi2 Liu Changjie
2026-07-23 15:48 ` [PATCH RESEND 2/9] dt-bindings: clock: stm32: add STM32H7RS RCC Liu Changjie
2026-07-26 16:21   ` sashiko-bot
2026-07-23 15:49 ` [PATCH RESEND 4/9] dt-bindings: pinctrl: stm32: add STM32H7RS Liu Changjie
2026-07-23 15:49 ` [PATCH RESEND 7/9] ARM: dts: stm32: add STM32H7R7 SoC Liu Changjie
2026-07-26 16:26   ` sashiko-bot [this message]
2026-07-23 15:49 ` [PATCH RESEND 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board Liu Changjie

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