* [PATCH RESEND 1/9] dt-bindings: arm: stm32: add Ruiside ART-Pi2
2026-07-26 15:49 [PATCH RESEND 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie
@ 2026-07-23 15:48 ` Liu Changjie
2026-07-23 15:48 ` [PATCH RESEND 2/9] dt-bindings: clock: stm32: add STM32H7RS RCC Liu Changjie
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Liu Changjie @ 2026-07-23 15:48 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel
Document the Ruiside vendor prefix and the ART-Pi2 board compatible.
The board is built around the STM32H7R7 microcontroller.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
---
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 3 +++
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
2 files changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index c6af3a463..337448dc4 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -50,6 +50,9 @@ properties:
- enum:
- st,stm32h750i-art-pi
- const: st,stm32h750
+ - items:
+ - const: ruiside,art-pi2
+ - const: st,stm32h7r7
- items:
- enum:
- st,stm32mp135f-dk
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 396044f36..401971b7f 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1425,6 +1425,8 @@ patternProperties:
description: Shenzhen Roofull Technology Co, Ltd
"^roseapplepi,.*":
description: RoseapplePi.org
+ "^ruiside,.*":
+ description: Shanghai Ruiside Electronic Technology Co., Ltd.
"^rve,.*":
description: Recharge Véhicule Électrique (RVE) inc.
"^saef,.*":
--
2.55.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH RESEND 2/9] dt-bindings: clock: stm32: add STM32H7RS RCC
2026-07-26 15:49 [PATCH RESEND 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie
2026-07-23 15:48 ` [PATCH RESEND 1/9] dt-bindings: arm: stm32: add Ruiside ART-Pi2 Liu Changjie
@ 2026-07-23 15:48 ` Liu Changjie
2026-07-26 16:21 ` sashiko-bot
2026-07-23 15:49 ` [PATCH RESEND 4/9] dt-bindings: pinctrl: stm32: add STM32H7RS Liu Changjie
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Liu Changjie @ 2026-07-23 15:48 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Lee Jones, Dario Binacchi
Cc: linux-clk, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, mfd
Extend the STM32 RCC binding for STM32H7RS and add its clock and
reset IDs. First-stage firmware configures the clock tree for
external-memory execution, so Linux consumes the active tree and
controls peripheral gates and resets.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
---
.../bindings/clock/st,stm32-rcc.yaml | 73 +++++++++++++++----
include/dt-bindings/clock/stm32h7rs-clks.h | 32 ++++++++
include/dt-bindings/mfd/stm32h7rs-rcc.h | 11 +++
3 files changed, 102 insertions(+), 14 deletions(-)
create mode 100644 include/dt-bindings/clock/stm32h7rs-clks.h
create mode 100644 include/dt-bindings/mfd/stm32h7rs-rcc.h
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
index f83a6120d..48a878c33 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
+++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
@@ -22,6 +22,7 @@ properties:
- st,stm32f42xx-rcc
- st,stm32f746-rcc
- st,stm32h743-rcc
+ - st,stm32h7rs-rcc
- const: st,stm32-rcc
- items:
- enum:
@@ -47,6 +48,10 @@ properties:
minItems: 2
maxItems: 3
+ clock-names:
+ minItems: 2
+ maxItems: 2
+
st,syscfg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@@ -79,14 +84,13 @@ required:
- '#reset-cells'
- '#clock-cells'
- clocks
- - st,syscfg
allOf:
- if:
properties:
compatible:
contains:
- const: st,stm32h743-rcc
+ const: st,stm32h7rs-rcc
then:
properties:
'#clock-cells':
@@ -97,23 +101,55 @@ allOf:
items:
- description: high speed external (HSE) clock input
- description: low speed external (LSE) clock input
- - description: Inter-IC sound (I2S) clock input
+ clock-names:
+ items:
+ - const: hse
+ - const: lse
+ st,syscfg: false
st,ssc-modfreq-hz: false
st,ssc-moddepth-permyriad: false
st,ssc-modmethod: false
+ required:
+ - clock-names
else:
- properties:
- '#clock-cells':
- const: 2
- description: |
- - The first cell is the clock type, possible values are 0 for
- gated clocks and 1 otherwise.
- - The second cell is the clock index for the specified type.
- clocks:
- items:
- - description: high speed external (HSE) clock input
- - description: Inter-IC sound (I2S) clock input
+ required:
+ - st,syscfg
+ allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32h743-rcc
+ then:
+ properties:
+ '#clock-cells':
+ const: 1
+ description: |
+ The clock index for the specified type.
+ clocks:
+ items:
+ - description: high speed external (HSE) clock input
+ - description: low speed external (LSE) clock input
+ - description: Inter-IC sound (I2S) clock input
+ clock-names: false
+ st,ssc-modfreq-hz: false
+ st,ssc-moddepth-permyriad: false
+ st,ssc-modmethod: false
+
+ else:
+ properties:
+ '#clock-cells':
+ const: 2
+ description: |
+ - The first cell is the clock type, possible values are 0 for
+ gated clocks and 1 otherwise.
+ - The second cell is the clock index for the specified type.
+ clocks:
+ items:
+ - description: high speed external (HSE) clock input
+ - description: Inter-IC sound (I2S) clock input
+ clock-names: false
additionalProperties: false
@@ -140,5 +176,14 @@ examples:
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
st,syscfg = <&pwrcfg>;
};
+ - |
+ reset-clock-controller@58024400 {
+ compatible = "st,stm32h7rs-rcc", "st,stm32-rcc";
+ reg = <0x58024400 0x400>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&clk_hse>, <&clk_lse>;
+ clock-names = "hse", "lse";
+ };
...
diff --git a/include/dt-bindings/clock/stm32h7rs-clks.h b/include/dt-bindings/clock/stm32h7rs-clks.h
new file mode 100644
index 000000000..e62e5d7e4
--- /dev/null
+++ b/include/dt-bindings/clock/stm32h7rs-clks.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+#ifndef _DT_BINDINGS_CLOCK_STM32H7RS_CLKS_H
+#define _DT_BINDINGS_CLOCK_STM32H7RS_CLKS_H
+
+#define STM32H7RS_SYS_CK 0
+#define STM32H7RS_HCLK 1
+#define STM32H7RS_PCLK1 2
+#define STM32H7RS_PCLK2 3
+#define STM32H7RS_PCLK4 4
+#define STM32H7RS_PCLK5 5
+
+#define STM32H7RS_TIM5_CK 6
+#define STM32H7RS_UART4_CK 7
+
+#define STM32H7RS_GPIOA_CK 8
+#define STM32H7RS_GPIOB_CK 9
+#define STM32H7RS_GPIOC_CK 10
+#define STM32H7RS_GPIOD_CK 11
+#define STM32H7RS_GPIOE_CK 12
+#define STM32H7RS_GPIOF_CK 13
+#define STM32H7RS_GPIOG_CK 14
+#define STM32H7RS_GPIOH_CK 15
+#define STM32H7RS_GPIOM_CK 16
+#define STM32H7RS_GPION_CK 17
+#define STM32H7RS_GPIOO_CK 18
+#define STM32H7RS_GPIOP_CK 19
+
+#define STM32H7RS_SDMMC1_CK 20
+
+#define STM32H7RS_MAX_CLKS 21
+
+#endif /* _DT_BINDINGS_CLOCK_STM32H7RS_CLKS_H */
diff --git a/include/dt-bindings/mfd/stm32h7rs-rcc.h b/include/dt-bindings/mfd/stm32h7rs-rcc.h
new file mode 100644
index 000000000..2302e0df1
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32h7rs-rcc.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+#ifndef _DT_BINDINGS_MFD_STM32H7RS_RCC_H
+#define _DT_BINDINGS_MFD_STM32H7RS_RCC_H
+
+/* AHB5 */
+#define STM32H7RS_RCC_AHB5_SDMMC1 8
+
+#define STM32H7RS_AHB5_RESET(bit) \
+ (STM32H7RS_RCC_AHB5_##bit + (0x7c * 8))
+
+#endif /* _DT_BINDINGS_MFD_STM32H7RS_RCC_H */
--
2.55.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH RESEND 4/9] dt-bindings: pinctrl: stm32: add STM32H7RS
2026-07-26 15:49 [PATCH RESEND 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie
2026-07-23 15:48 ` [PATCH RESEND 1/9] dt-bindings: arm: stm32: add Ruiside ART-Pi2 Liu Changjie
2026-07-23 15:48 ` [PATCH RESEND 2/9] dt-bindings: clock: stm32: add STM32H7RS RCC Liu Changjie
@ 2026-07-23 15:49 ` Liu Changjie
2026-07-23 15:49 ` [PATCH RESEND 7/9] ARM: dts: stm32: add STM32H7R7 SoC Liu Changjie
2026-07-23 15:49 ` [PATCH RESEND 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board Liu Changjie
4 siblings, 0 replies; 8+ messages in thread
From: Liu Changjie @ 2026-07-23 15:49 UTC (permalink / raw)
To: Antonio Borneo, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maxime Coquelin, Alexandre Torgue
Cc: linux-gpio, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel
Add the STM32H7RS pin controller compatible. The H7RS family exposes
GPIO banks M through P, so extend the bank names and EXTI I/O port
selector range accordingly.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
---
.../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
index 76d956b4a..6e74485b1 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -24,6 +24,7 @@ properties:
- st,stm32f746-pinctrl
- st,stm32f769-pinctrl
- st,stm32h743-pinctrl
+ - st,stm32h7rs-pinctrl
- st,stm32mp135-pinctrl
- st,stm32mp157-pinctrl
- st,stm32mp157-z-pinctrl
@@ -115,6 +116,10 @@ patternProperties:
- GPIOI
- GPIOJ
- GPIOK
+ - GPIOM
+ - GPION
+ - GPIOO
+ - GPIOP
- GPIOZ
st,bank-ioport:
@@ -123,7 +128,7 @@ patternProperties:
to select GPIOs as interrupts).
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
- maximum: 11
+ maximum: 15
patternProperties:
"^(.+-hog(-[0-9]+)?)$":
--
2.55.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH RESEND 7/9] ARM: dts: stm32: add STM32H7R7 SoC
2026-07-26 15:49 [PATCH RESEND 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie
` (2 preceding siblings ...)
2026-07-23 15:49 ` [PATCH RESEND 4/9] dt-bindings: pinctrl: stm32: add STM32H7RS Liu Changjie
@ 2026-07-23 15:49 ` Liu Changjie
2026-07-26 16:26 ` sashiko-bot
2026-07-23 15:49 ` [PATCH RESEND 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board Liu Changjie
4 siblings, 1 reply; 8+ messages in thread
From: Liu Changjie @ 2026-07-23 15:49 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel
Describe the Cortex-M7 CPU, clocks, TIM5 clockevent, UART4, SDMMC1,
EXTI, system configuration controller and GPIO banks available on
STM32H7R7 devices. Expose the RCC reset controller for peripheral
consumers.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
---
arch/arm/boot/dts/st/stm32h7r7.dtsi | 255 ++++++++++++++++++++++++++++
1 file changed, 255 insertions(+)
create mode 100644 arch/arm/boot/dts/st/stm32h7r7.dtsi
diff --git a/arch/arm/boot/dts/st/stm32h7r7.dtsi b/arch/arm/boot/dts/st/stm32h7r7.dtsi
new file mode 100644
index 000000000..ad25dddbe
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32h7r7.dtsi
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+#include "../armv7-m.dtsi"
+#include <dt-bindings/clock/stm32h7rs-clks.h>
+#include <dt-bindings/mfd/stm32h7rs-rcc.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-m7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&rcc STM32H7RS_SYS_CK>;
+ };
+ };
+
+ clocks {
+ clk_hse: clock-hse {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ clk_lse: clock-lse {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ soc {
+ timer5: timer@40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <54>;
+ clocks = <&rcc STM32H7RS_TIM5_CK>;
+ };
+
+ uart4: serial@40004c00 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40004c00 0x400>;
+ interrupts = <85>;
+ clocks = <&rcc STM32H7RS_UART4_CK>;
+ status = "disabled";
+ };
+
+ sdmmc1: mmc@52007000 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x",
+ "arm,primecell";
+ arm,primecell-periphid = <0x00253180>;
+ reg = <0x52007000 0x1000>;
+ interrupts = <108>;
+ clocks = <&rcc STM32H7RS_SDMMC1_CK>;
+ clock-names = "apb_pclk";
+ resets = <&rcc STM32H7RS_AHB5_RESET(SDMMC1)>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
+ };
+
+ exti: interrupt-controller@58000000 {
+ compatible = "st,stm32h7-exti";
+ reg = <0x58000000 0x400>;
+ interrupts = <16>, <17>, <18>, <19>,
+ <20>, <21>, <22>, <23>,
+ <24>, <25>, <26>, <27>,
+ <28>, <29>, <30>, <31>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ syscfg: syscon@58000400 {
+ compatible = "st,stm32-syscfg", "syscon";
+ reg = <0x58000400 0x400>;
+ };
+
+ pinctrl: pinctrl@58020000 {
+ compatible = "st,stm32h7rs-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x58020000 0x4000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x130>;
+
+ gpioa: gpio@58020000 {
+ reg = <0x0 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOA_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ st,bank-name = "GPIOA";
+ };
+
+ gpiob: gpio@58020400 {
+ reg = <0x400 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOB_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ st,bank-name = "GPIOB";
+ };
+
+ gpioc: gpio@58020800 {
+ reg = <0x800 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOC_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ st,bank-name = "GPIOC";
+ };
+
+ gpiod: gpio@58020c00 {
+ reg = <0xc00 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOD_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ st,bank-name = "GPIOD";
+ };
+
+ gpioe: gpio@58021000 {
+ reg = <0x1000 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOE_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ st,bank-name = "GPIOE";
+ };
+
+ gpiof: gpio@58021400 {
+ reg = <0x1400 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOF_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ st,bank-name = "GPIOF";
+ };
+
+ gpiog: gpio@58021800 {
+ reg = <0x1800 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOG_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ st,bank-name = "GPIOG";
+ };
+
+ gpioh: gpio@58021c00 {
+ reg = <0x1c00 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOH_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ st,bank-name = "GPIOH";
+ };
+
+ gpiom: gpio@58023000 {
+ reg = <0x3000 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOM_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 192 16>;
+ st,bank-name = "GPIOM";
+ };
+
+ gpion: gpio@58023400 {
+ reg = <0x3400 0x400>;
+ clocks = <&rcc STM32H7RS_GPION_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 208 16>;
+ st,bank-name = "GPION";
+ };
+
+ gpioo: gpio@58023800 {
+ reg = <0x3800 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOO_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 224 16>;
+ st,bank-name = "GPIOO";
+ };
+
+ gpiop: gpio@58023c00 {
+ reg = <0x3c00 0x400>;
+ clocks = <&rcc STM32H7RS_GPIOP_CK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 240 16>;
+ st,bank-name = "GPIOP";
+ };
+ };
+
+ rcc: reset-clock-controller@58024400 {
+ compatible = "st,stm32h7rs-rcc", "st,stm32-rcc";
+ reg = <0x58024400 0x400>;
+ clocks = <&clk_hse>, <&clk_lse>;
+ clock-names = "hse", "lse";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ };
+};
+
+&nvic {
+ arm,num-irq-priority-bits = <4>;
+};
+
+&systick {
+ clock-frequency = <250000000>;
+ status = "okay";
+};
--
2.55.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH RESEND 7/9] ARM: dts: stm32: add STM32H7R7 SoC
2026-07-23 15:49 ` [PATCH RESEND 7/9] ARM: dts: stm32: add STM32H7R7 SoC Liu Changjie
@ 2026-07-26 16:26 ` sashiko-bot
0 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-07-26 16:26 UTC (permalink / raw)
To: Liu Changjie; +Cc: conor+dt, devicetree, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Mismatch between unit-address and `reg` property in GPIO bank nodes within the `pinctrl` block.
--
--- Patch [7]: [PATCH RESEND 7/9] ARM: dts: stm32: add STM32H7R7 SoC ---
commit e7124a5b13abf93e1321e7a33e469a82c2e13c42
Author: Liu Changjie <liucj1228@outlook.com>
ARM: dts: stm32: add STM32H7R7 SoC
This commit adds the device tree include file for the STM32H7R7 SoC. It
describes the CPU, clocks, timers, UART, SDMMC, and various GPIO banks within
the pinctrl block.
> diff --git a/arch/arm/boot/dts/st/stm32h7r7.dtsi b/arch/arm/boot/dts/st/stm32h7r7.dtsi
> new file mode 100644
> index 0000000000000..ad25dddbe6ed8
> --- /dev/null
> +++ b/arch/arm/boot/dts/st/stm32h7r7.dtsi
[ ... ]
> + pinctrl: pinctrl@58020000 {
> + compatible = "st,stm32h7rs-pinctrl";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x58020000 0x4000>;
> + interrupt-parent = <&exti>;
> + st,syscfg = <&syscfg 0x130>;
> +
> + gpioa: gpio@58020000 {
> + reg = <0x0 0x400>;
[Severity: Low]
Should the unit-address match the first address specified in the reg
property? Because the parent pinctrl node sets ranges = <0 0x58020000 0x4000>,
the child nodes' reg properties are relative to 0. Would it be better to use
gpio@0 instead of gpio@58020000 to avoid dtc -Wunit_address_vs_reg warnings?
This pattern appears to repeat for the subsequent GPIO banks as well, such as
gpiob: gpio@58020400 having reg = <0x400 0x400>.
--
Sashiko AI review · https://sashiko.dev/#/patchset/MN0PR19MB60912FA1E75E4E55B2E27D34ACCD2@MN0PR19MB6091.namprd19.prod.outlook.com?part=7
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH RESEND 8/9] ARM: dts: stm32: add Ruiside ART-Pi2 board
2026-07-26 15:49 [PATCH RESEND 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support Liu Changjie
` (3 preceding siblings ...)
2026-07-23 15:49 ` [PATCH RESEND 7/9] ARM: dts: stm32: add STM32H7R7 SoC Liu Changjie
@ 2026-07-23 15:49 ` Liu Changjie
4 siblings, 0 replies; 8+ messages in thread
From: Liu Changjie @ 2026-07-23 15:49 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue
Cc: devicetree, linux-kernel, linux-stm32, linux-arm-kernel
Add the STM32H7R7-based ART-Pi2 with 32 MiB of external HyperRAM,
UART4 console pin configuration, user LEDs on PO1 and PO5, and the
user button on PC13. Enable the four-bit microSD slot and reserve a
coherent DMA pool for noMMU DMA allocations.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
---
arch/arm/boot/dts/st/Makefile | 1 +
arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts | 100 +++++++++++++++++++
arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi | 63 ++++++++++++
3 files changed, 164 insertions(+)
create mode 100644 arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts
create mode 100644 arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile
index 10c5d75f6..ae27a4ef9 100644
--- a/arch/arm/boot/dts/st/Makefile
+++ b/arch/arm/boot/dts/st/Makefile
@@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32h743i-disco.dtb \
stm32h747i-disco.dtb \
stm32h750i-art-pi.dtb \
+ stm32h7r7l8-art-pi2.dtb \
stm32mp133c-prihmb.dtb \
stm32mp135f-dhcor-dhsbc.dtb \
stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtb \
diff --git a/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts b/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts
new file mode 100644
index 000000000..ead141817
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+/dts-v1/;
+
+#include "stm32h7r7.dtsi"
+#include "stm32h7rs-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "RT-Thread ART-Pi2 STM32H7R7 board";
+ compatible = "ruiside,art-pi2", "st,stm32h7r7";
+
+ chosen {
+ bootargs = "earlycon console=ttySTM0,115200";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@90000000 {
+ device_type = "memory";
+ reg = <0x90000000 0x02000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dma_pool: dma-pool {
+ compatible = "shared-dma-pool";
+ no-map;
+ size = <0x00200000>;
+ linux,dma-default;
+ };
+ };
+
+ aliases {
+ mmc0 = &sdmmc1;
+ serial0 = &uart4;
+ };
+
+ v3v3: regulator-v3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_red: led-red {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpioo 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_blue: led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpioo 5 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-user {
+ label = "User";
+ linux,code = <KEY_WAKEUP>;
+ gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart4 {
+ pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ max-frequency = <50000000>;
+ status = "okay";
+};
+
+&clk_hse {
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi
new file mode 100644
index 000000000..08f09f562
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) 2026 Liu Changjie <liucj1228@outlook.com>
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+&pinctrl {
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF11)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF11)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF11)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF11)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, AF11)>; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF11)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF11)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF11)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF11)>; /* SDMMC1_CK */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF11)>; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ uart4_pins_a: uart4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, AF8)>, /* UART4_RX */
+ <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+};
--
2.55.0
^ permalink raw reply related [flat|nested] 8+ messages in thread