From: sashiko-bot@kernel.org
To: "Yu-Chun Lin" <eleanor.lin@realtek.com>
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v11 04/11] clk: realtek: Introduce a common probe()
Date: Tue, 28 Jul 2026 14:41:51 +0000 [thread overview]
Message-ID: <20260728144151.B96D21F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260728142806.1954638-5-eleanor.lin@realtek.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The clock registration loop does not check for ERR_PTR values in the hw array, which will cause a kernel panic if a clock is intentionally omitted.
- [Medium] The clock provider is exposed to the system before the probe is fully complete, risking exposure of an orphaned clock on error paths.
--
--- Patch [4]: [PATCH v11 04/11] clk: realtek: Introduce a common probe() ---
commit 1821fe944a61d09ec77d386cf175a9aadc142c21
Author: Cheng-Yu Lee <cylee12@realtek.com>
clk: realtek: Introduce a common probe()
Add rtk_clk_probe() to set up the shared regmap, register clock hardware,
and add the clock provider. It also creates an auxiliary device for the
reset driver if the "#reset-cells" property is present.
> diff --git a/drivers/clk/realtek/clk-rtk-common.c b/drivers/clk/realtek/clk-rtk-common.c
> new file mode 100644
> index 0000000000000..86adeedbdeada
> --- /dev/null
> +++ b/drivers/clk/realtek/clk-rtk-common.c
[ ... ]
> +int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc)
> +{
[ ... ]
> + for (i = 0; i < desc->clk_data->num; i++) {
> + hw = desc->clk_data->hws[i];
> + if (!hw)
> + continue;
> +
> + ret = devm_clk_hw_register(dev, hw);
[Severity: High]
Will this loop crash if the hw array contains ERR_PTR(-ENOENT)?
In clock drivers, the clk_hw_onecell_data::hws array often contains
ERR_PTR(-ENOENT) for clock indices that are intentionally omitted or
unsupported on specific SoC variants.
Since the check only looks for NULL, an ERR_PTR would bypass this check and
be passed to devm_clk_hw_register(). This typically causes a panic when
clk_hw_register() attempts to dereference the pointer.
Would it be better to check for IS_ERR_OR_NULL(hw) here?
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to register hw of clk%d\n", i);
> + }
> +
> + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> + desc->clk_data);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to add clock provider\n");
> +
> + return rtk_reset_controller_register(dev, desc->aux_name, regmap);
[Severity: Medium]
Is there a risk of exposing an orphaned clock on the error path here?
The clock provider is registered via devm_of_clk_add_hw_provider() before
rtk_reset_controller_register() is called. If the reset controller
registration fails, the probe aborts and devres unregisters the clock
provider.
During the window between registration and cleanup, concurrent consumers
could look up and acquire the clocks, only for them to be unregistered
immediately. This leaves consumers with orphaned clocks that cannot
properly control the hardware.
Would it be safer to make the clock provider registration the very last step
of the probe function?
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260728142806.1954638-1-eleanor.lin@realtek.com?part=4
next prev parent reply other threads:[~2026-07-28 14:41 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-28 14:27 [PATCH v11 00/11] clk / reset: realtek: Add RTD1625 clock and reset support Yu-Chun Lin
2026-07-28 14:27 ` [PATCH v11 01/11] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Yu-Chun Lin
2026-07-28 14:27 ` [PATCH v11 02/11] reset: Add Realtek basic reset support Yu-Chun Lin
2026-07-28 14:27 ` [PATCH v11 03/11] reset: realtek: Add RTD1625 reset controller driver Yu-Chun Lin
2026-07-28 14:51 ` sashiko-bot
2026-07-28 14:27 ` [PATCH v11 04/11] clk: realtek: Introduce a common probe() Yu-Chun Lin
2026-07-28 14:41 ` sashiko-bot [this message]
2026-07-28 14:28 ` [PATCH v11 05/11] clk: realtek: Add support for phase locked loops (PLLs) Yu-Chun Lin
2026-07-28 14:41 ` sashiko-bot
2026-07-28 14:28 ` [PATCH v11 06/11] clk: realtek: Add support for gate clock Yu-Chun Lin
2026-07-28 14:28 ` [PATCH v11 07/11] clk: realtek: Add support for mux clock Yu-Chun Lin
2026-07-28 14:28 ` [PATCH v11 08/11] clk: realtek: Add support for MMC-tuned PLL clocks Yu-Chun Lin
2026-07-28 14:40 ` sashiko-bot
2026-07-28 14:28 ` [PATCH v11 09/11] clk: realtek: Add RTD1625-CRT clock controller driver Yu-Chun Lin
2026-07-28 14:28 ` [PATCH v11 10/11] clk: realtek: Add RTD1625-ISO " Yu-Chun Lin
2026-07-28 14:28 ` [PATCH v11 11/11] arm64: dts: realtek: Add clock support for RTD1625 Yu-Chun Lin
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