* [PATCH v4 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros
2026-07-28 15:49 [PATCH v4 0/4] Add ADC support for lemans, monaco and hamoa Jishnu Prakash
@ 2026-07-28 15:49 ` Jishnu Prakash
2026-07-28 16:00 ` sashiko-bot
2026-07-28 15:49 ` [PATCH v4 2/4] arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au Jishnu Prakash
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Jishnu Prakash @ 2026-07-28 15:49 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Ayyagari Ushasreevalli,
Kamal Wadhwa, Loic Poulain, Jishnu Prakash, Konrad Dybcio
Add macro definitions for virtual channels (combination of ADC channel
number and PMIC SID number), to be used in devicetree by clients of ADC5
GEN3 device and in the "reg" property of ADC channels.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h | 88 +++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h
new file mode 100644
index 000000000000..aa8e54d7e786
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DTS_ARM64_QCOM_ADC5_GEN3_H__
+#define __DTS_ARM64_QCOM_ADC5_GEN3_H__
+
+/* ADC channels for PMIC5 Gen3 */
+
+#define VIRT_CHAN(sid, chan) ((sid) << 8 | (chan))
+
+#define ADC5_GEN3_REF_GND(sid) VIRT_CHAN(sid, 0x00)
+#define ADC5_GEN3_1P25VREF(sid) VIRT_CHAN(sid, 0x01)
+#define ADC5_GEN3_VREF_VADC(sid) VIRT_CHAN(sid, 0x02)
+#define ADC5_GEN3_DIE_TEMP(sid) VIRT_CHAN(sid, 0x03)
+
+#define ADC5_GEN3_AMUX1_THM(sid) VIRT_CHAN(sid, 0x04)
+#define ADC5_GEN3_AMUX2_THM(sid) VIRT_CHAN(sid, 0x05)
+#define ADC5_GEN3_AMUX3_THM(sid) VIRT_CHAN(sid, 0x06)
+#define ADC5_GEN3_AMUX4_THM(sid) VIRT_CHAN(sid, 0x07)
+#define ADC5_GEN3_AMUX5_THM(sid) VIRT_CHAN(sid, 0x08)
+#define ADC5_GEN3_AMUX6_THM(sid) VIRT_CHAN(sid, 0x09)
+#define ADC5_GEN3_AMUX1_GPIO(sid) VIRT_CHAN(sid, 0x0a)
+#define ADC5_GEN3_AMUX2_GPIO(sid) VIRT_CHAN(sid, 0x0b)
+#define ADC5_GEN3_AMUX3_GPIO(sid) VIRT_CHAN(sid, 0x0c)
+#define ADC5_GEN3_AMUX4_GPIO(sid) VIRT_CHAN(sid, 0x0d)
+
+#define ADC5_GEN3_CHG_TEMP(sid) VIRT_CHAN(sid, 0x10)
+#define ADC5_GEN3_USB_SNS_V_16(sid) VIRT_CHAN(sid, 0x11)
+#define ADC5_GEN3_VIN_DIV16_MUX(sid) VIRT_CHAN(sid, 0x12)
+#define ADC5_GEN3_VREF_BAT_THERM(sid) VIRT_CHAN(sid, 0x15)
+#define ADC5_GEN3_IIN_FB(sid) VIRT_CHAN(sid, 0x17)
+#define ADC5_GEN3_TEMP_ALARM_LITE(sid) VIRT_CHAN(sid, 0x18)
+#define ADC5_GEN3_IIN_SMB(sid) VIRT_CHAN(sid, 0x19)
+#define ADC5_GEN3_ICHG_SMB(sid) VIRT_CHAN(sid, 0x1b)
+#define ADC5_GEN3_ICHG_FB(sid) VIRT_CHAN(sid, 0xa1)
+
+/* 30k pull-up */
+#define ADC5_GEN3_AMUX1_THM_30K_PU(sid) VIRT_CHAN(sid, 0x24)
+#define ADC5_GEN3_AMUX2_THM_30K_PU(sid) VIRT_CHAN(sid, 0x25)
+#define ADC5_GEN3_AMUX3_THM_30K_PU(sid) VIRT_CHAN(sid, 0x26)
+#define ADC5_GEN3_AMUX4_THM_30K_PU(sid) VIRT_CHAN(sid, 0x27)
+#define ADC5_GEN3_AMUX5_THM_30K_PU(sid) VIRT_CHAN(sid, 0x28)
+#define ADC5_GEN3_AMUX6_THM_30K_PU(sid) VIRT_CHAN(sid, 0x29)
+#define ADC5_GEN3_AMUX1_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2a)
+#define ADC5_GEN3_AMUX2_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2b)
+#define ADC5_GEN3_AMUX3_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2c)
+#define ADC5_GEN3_AMUX4_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2d)
+
+/* 100k pull-up */
+#define ADC5_GEN3_AMUX1_THM_100K_PU(sid) VIRT_CHAN(sid, 0x44)
+#define ADC5_GEN3_AMUX2_THM_100K_PU(sid) VIRT_CHAN(sid, 0x45)
+#define ADC5_GEN3_AMUX3_THM_100K_PU(sid) VIRT_CHAN(sid, 0x46)
+#define ADC5_GEN3_AMUX4_THM_100K_PU(sid) VIRT_CHAN(sid, 0x47)
+#define ADC5_GEN3_AMUX5_THM_100K_PU(sid) VIRT_CHAN(sid, 0x48)
+#define ADC5_GEN3_AMUX6_THM_100K_PU(sid) VIRT_CHAN(sid, 0x49)
+#define ADC5_GEN3_AMUX1_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4a)
+#define ADC5_GEN3_AMUX2_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4b)
+#define ADC5_GEN3_AMUX3_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4c)
+#define ADC5_GEN3_AMUX4_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4d)
+
+/* 400k pull-up */
+#define ADC5_GEN3_AMUX1_THM_400K_PU(sid) VIRT_CHAN(sid, 0x64)
+#define ADC5_GEN3_AMUX2_THM_400K_PU(sid) VIRT_CHAN(sid, 0x65)
+#define ADC5_GEN3_AMUX3_THM_400K_PU(sid) VIRT_CHAN(sid, 0x66)
+#define ADC5_GEN3_AMUX4_THM_400K_PU(sid) VIRT_CHAN(sid, 0x67)
+#define ADC5_GEN3_AMUX5_THM_400K_PU(sid) VIRT_CHAN(sid, 0x68)
+#define ADC5_GEN3_AMUX6_THM_400K_PU(sid) VIRT_CHAN(sid, 0x69)
+#define ADC5_GEN3_AMUX1_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6a)
+#define ADC5_GEN3_AMUX2_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6b)
+#define ADC5_GEN3_AMUX3_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6c)
+#define ADC5_GEN3_AMUX4_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6d)
+
+/* 1/3 Divider */
+#define ADC5_GEN3_AMUX1_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8a)
+#define ADC5_GEN3_AMUX2_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8b)
+#define ADC5_GEN3_AMUX3_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8c)
+#define ADC5_GEN3_AMUX4_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8d)
+
+#define ADC5_GEN3_VPH_PWR(sid) VIRT_CHAN(sid, 0x8e)
+#define ADC5_GEN3_VBAT_SNS_QBG(sid) VIRT_CHAN(sid, 0x8f)
+
+#define ADC5_GEN3_VBAT_SNS_CHGR(sid) VIRT_CHAN(sid, 0x94)
+#define ADC5_GEN3_VBAT_2S_MID_QBG(sid) VIRT_CHAN(sid, 0x96)
+#define ADC5_GEN3_VBAT_2S_MID_CHGR(sid) VIRT_CHAN(sid, 0x9d)
+
+#endif /* __DTS_ARM64_QCOM_ADC5_GEN3_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros
2026-07-28 15:49 ` [PATCH v4 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros Jishnu Prakash
@ 2026-07-28 16:00 ` sashiko-bot
0 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-07-28 16:00 UTC (permalink / raw)
To: Jishnu Prakash; +Cc: robh, conor+dt, devicetree
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Device tree binding header is improperly placed in an architecture-specific directory instead of `include/dt-bindings/`.
- [Medium] Function-like macros share exact names with object-like macros used in the driver, causing preprocessor namespace collisions.
--
--- Patch [1]: [PATCH v4 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros ---
commit 59d21969abff768469fefb21430c2e819299df4b
Author: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros
This commit adds macro definitions for virtual channels (combining the
ADC channel number and PMIC SID number) to be used in the devicetree by
clients of the ADC5 GEN3 device.
> diff --git a/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h
> new file mode 100644
> index 0000000000000..aa8e54d7e786a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h
> @@ -0,0 +1,88 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef __DTS_ARM64_QCOM_ADC5_GEN3_H__
[Severity: Medium]
Should this device tree binding header be placed in include/dt-bindings/
instead of arch/arm64/boot/dts/qcom/?
Headers that define hardware channel IDs form the ABI between the devicetree
and the operating system drivers. Placing this in an architecture-specific
directory makes it inaccessible to C drivers or other architectures.
Moving it to include/dt-bindings/ would allow it to be shared universally and
parsed by standard DT schema validation tools. The include guard also appears
to couple the file unnecessarily to ARM64.
> +#define __DTS_ARM64_QCOM_ADC5_GEN3_H__
> +
> +/* ADC channels for PMIC5 Gen3 */
> +
> +#define VIRT_CHAN(sid, chan) ((sid) << 8 | (chan))
> +
> +#define ADC5_GEN3_REF_GND(sid) VIRT_CHAN(sid, 0x00)
[Severity: Medium]
Will this function-like macro collide with the object-like macros already
used in the driver?
The corresponding IIO ADC driver already uses identically named object-like
macros, such as #define ADC5_GEN3_REF_GND 0x00.
If the C driver includes this header to avoid duplicating channel
definitions, using the exact same identifier for both a function-like macro
and an object-like macro will trigger preprocessor redefinition errors.
Could the base channel IDs be defined as object-like constants, and a
distinctly named helper macro be provided to construct the virtual channel?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260728-adc5_gen3_dt-v4-0-355f0edece77@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 2/4] arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au
2026-07-28 15:49 [PATCH v4 0/4] Add ADC support for lemans, monaco and hamoa Jishnu Prakash
2026-07-28 15:49 ` [PATCH v4 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros Jishnu Prakash
@ 2026-07-28 15:49 ` Jishnu Prakash
2026-07-28 15:49 ` [PATCH v4 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU Jishnu Prakash
2026-07-28 15:49 ` [PATCH v4 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support Jishnu Prakash
3 siblings, 0 replies; 8+ messages in thread
From: Jishnu Prakash @ 2026-07-28 15:49 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Ayyagari Ushasreevalli,
Kamal Wadhwa, Loic Poulain, Jishnu Prakash, Konrad Dybcio
From: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Add ADC nodes for the four PMM8654au PMICs (pmm8654au_0 through
pmm8654au_3) on the Lemans platform.
Each ADC node exposes the following ADC channels:
- DIE_TEMP: PMIC die temperature channel
- VPH_PWR: Battery/supply voltage channel
Also add the io-channels and io-channel-names properties under
the temp-alarm nodes so that they can get temperature reading
from the ADC die_temp channels.
Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-pmics.dtsi | 93 ++++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi
index 341119fc8244..500f715931aa 100644
--- a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/spmi/spmi.h>
+#include "qcom-adc5-gen3.h"
/ {
thermal-zones {
@@ -110,6 +111,8 @@ pmm8654au_0_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmm8654au_0_adc ADC5_GEN3_DIE_TEMP(0)>;
+ io-channel-names = "thermal";
};
pmm8654au_0_pon: pon@1200 {
@@ -141,6 +144,27 @@ pmm8654au_0_rtc: rtc@6100 {
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};
+ pmm8654au_0_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ interrupts-extended = <&spmi_bus 0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@3 {
+ reg = <ADC5_GEN3_DIE_TEMP(0)>;
+ label = "pmm8654au_0_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@8e {
+ reg = <ADC5_GEN3_VPH_PWR(0)>;
+ label = "pmm8654au_0_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
pmm8654au_0_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
@@ -176,6 +200,29 @@ pmm8654au_1_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmm8654au_1_adc ADC5_GEN3_DIE_TEMP(2)>;
+ io-channel-names = "thermal";
+ };
+
+ pmm8654au_1_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ interrupts-extended = <&spmi_bus 0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@203 {
+ reg = <ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pmm8654au_1_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@28e {
+ reg = <ADC5_GEN3_VPH_PWR(2)>;
+ label = "pmm8654au_1_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
};
pmm8654au_1_gpios: gpio@8800 {
@@ -200,6 +247,29 @@ pmm8654au_2_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmm8654au_2_adc ADC5_GEN3_DIE_TEMP(4)>;
+ io-channel-names = "thermal";
+ };
+
+ pmm8654au_2_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ interrupts-extended = <&spmi_bus 0x4 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@403 {
+ reg = <ADC5_GEN3_DIE_TEMP(4)>;
+ label = "pmm8654au_2_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@48e {
+ reg = <ADC5_GEN3_VPH_PWR(4)>;
+ label = "pmm8654au_2_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
};
pmm8654au_2_gpios: gpio@8800 {
@@ -224,6 +294,29 @@ pmm8654au_3_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmm8654au_3_adc ADC5_GEN3_DIE_TEMP(6)>;
+ io-channel-names = "thermal";
+ };
+
+ pmm8654au_3_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ interrupts-extended = <&spmi_bus 0x6 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@603 {
+ reg = <ADC5_GEN3_DIE_TEMP(6)>;
+ label = "pmm8654au_3_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@68e {
+ reg = <ADC5_GEN3_VPH_PWR(6)>;
+ label = "pmm8654au_3_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
};
pmm8654au_3_gpios: gpio@8800 {
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU
2026-07-28 15:49 [PATCH v4 0/4] Add ADC support for lemans, monaco and hamoa Jishnu Prakash
2026-07-28 15:49 ` [PATCH v4 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros Jishnu Prakash
2026-07-28 15:49 ` [PATCH v4 2/4] arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au Jishnu Prakash
@ 2026-07-28 15:49 ` Jishnu Prakash
2026-07-28 16:16 ` sashiko-bot
2026-07-28 15:49 ` [PATCH v4 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support Jishnu Prakash
3 siblings, 1 reply; 8+ messages in thread
From: Jishnu Prakash @ 2026-07-28 15:49 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Ayyagari Ushasreevalli,
Kamal Wadhwa, Loic Poulain, Jishnu Prakash, Konrad Dybcio
From: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Add ADC nodes for PMM8620AU PMIC instances (SID 0 and SID 2)
present on the Monaco platform.
Each ADC node exposes the following ADC channels:
- DIE_TEMP: PMIC die temperature channel
- VPH_PWR: Battery/supply voltage channel
Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Tested-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco-pmics.dtsi | 43 ++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
index e990d7367719..6e096b9b7546 100644
--- a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/spmi/spmi.h>
+#include "qcom-adc5-gen3.h"
&spmi_bus {
pmm8620au_0: pmic@0 {
@@ -20,6 +21,27 @@ pmm8620au_0_rtc: rtc@6100 {
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};
+ pmm8620au_0_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ interrupts-extended = <&spmi_bus 0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@3 {
+ reg = <ADC5_GEN3_DIE_TEMP(0)>;
+ label = "pmm8620au_0_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@8e {
+ reg = <ADC5_GEN3_VPH_PWR(0)>;
+ label = "pmm8620au_0_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
pmm8620au_0_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
@@ -37,6 +59,27 @@ pmm8650au_1: pmic@2 {
#address-cells = <1>;
#size-cells = <0>;
+ pmm8650au_1_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ interrupts-extended = <&spmi_bus 0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@203 {
+ reg = <ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pmm8650au_1_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@28e {
+ reg = <ADC5_GEN3_VPH_PWR(2)>;
+ label = "pmm8650au_1_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
pmm8650au_1_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU
2026-07-28 15:49 ` [PATCH v4 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU Jishnu Prakash
@ 2026-07-28 16:16 ` sashiko-bot
0 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-07-28 16:16 UTC (permalink / raw)
To: Jishnu Prakash; +Cc: devicetree, conor+dt, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message inaccurately claims that both SID 0 and SID 2 are PMM8620AU PMIC instances, whereas the device tree correctly uses PMM8650AU for SID 2.
--
--- Patch [3]: [PATCH v4 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU ---
commit 07dcd0ba34ae862d89be0793a9dab759b0361ee1
Author: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU
This commit adds ADC nodes for PMIC instances on the Monaco platform. The
new nodes expose the die temperature and supply voltage channels.
> Add ADC nodes for PMM8620AU PMIC instances (SID 0 and SID 2)
> present on the Monaco platform.
[Severity: Medium]
Is this description accurate? The commit message states that both SID 0 and
SID 2 are PMM8620AU PMIC instances.
Looking at the added device tree nodes, the PMIC at SID 2 (pmic@2) is named
pmm8650au_1 and its ADC node is named pmm8650au_1_adc, which indicates it is
a PMM8650AU instance rather than PMM8620AU.
Could the commit message be updated to correctly reflect the hardware being
modified for SID 2?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260728-adc5_gen3_dt-v4-0-355f0edece77@oss.qualcomm.com?part=3
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support
2026-07-28 15:49 [PATCH v4 0/4] Add ADC support for lemans, monaco and hamoa Jishnu Prakash
` (2 preceding siblings ...)
2026-07-28 15:49 ` [PATCH v4 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU Jishnu Prakash
@ 2026-07-28 15:49 ` Jishnu Prakash
2026-07-28 16:29 ` sashiko-bot
3 siblings, 1 reply; 8+ messages in thread
From: Jishnu Prakash @ 2026-07-28 15:49 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Ayyagari Ushasreevalli,
Kamal Wadhwa, Loic Poulain, Jishnu Prakash
From: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Add ADC node and define channels for:
- Die temperature for PMK8550, PM8550VE* and PMC8380* PMICs.
- PM8550: Die temperature, VPH power, and system thermistors.
Add io-channels and io-channel-names properties to the
temp_alarm nodes so that they can get temperature reading
from the ADC die_temp channels.
Remove die_temp channel of PMC8380_6 for Purwa boards where
this PMIC is not present.
Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 158 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 1 +
.../boot/dts/qcom/x1p42100-asus-vivobook-s15.dts | 1 +
.../boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi | 1 +
arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 1 +
.../boot/dts/qcom/x1p42100-hp-omnibook-x14.dts | 1 +
.../boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 1 +
7 files changed, 164 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
index 6a31a0adf8be..17d754d57e18 100644
--- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
@@ -6,7 +6,9 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/spmi/spmi.h>
+#include "qcom-adc5-gen3.h"
/ {
thermal-zones {
@@ -277,6 +279,134 @@ pmk8550_pwm: pwm {
status = "disabled";
};
+
+ pmk8550_vadc: adc@9000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x9000>, <0x9100>;
+ interrupts-extended = <&spmi_bus0 0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
+ <&spmi_bus0 0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ pinctrl-0 = <&sys_therm_0_gpio3>, <&sys_therm_1_gpio4>;
+ pinctrl-names = "default";
+
+ channel@3 {
+ reg = <ADC5_GEN3_DIE_TEMP(0)>;
+ label = "pmk8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@103 {
+ reg = <ADC5_GEN3_DIE_TEMP(1)>;
+ label = "pm8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@144 {
+ reg = <ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+ label = "pm8550_therm_2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@145 {
+ reg = <ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+ label = "pm8550_therm_3";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@146 {
+ reg = <ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+ label = "pm8550_therm_4";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@147 {
+ reg = <ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+ label = "pm8550_therm_5";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@148 {
+ reg = <ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+ label = "pm8550_therm_6";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@14a {
+ reg = <ADC5_GEN3_AMUX1_GPIO_100K_PU(1)>;
+ label = "pm8550_gpio_01";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@14b {
+ reg = <ADC5_GEN3_AMUX2_GPIO_100K_PU(1)>;
+ label = "pm8550_gpio_02";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@18e {
+ reg = <ADC5_GEN3_VPH_PWR(1)>;
+ label = "pm8550_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ channel@203 {
+ reg = <ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pm8550ve_2_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@303 {
+ reg = <ADC5_GEN3_DIE_TEMP(3)>;
+ label = "pmc8380_3_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@403 {
+ reg = <ADC5_GEN3_DIE_TEMP(4)>;
+ label = "pmc8380_4_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@503 {
+ reg = <ADC5_GEN3_DIE_TEMP(5)>;
+ label = "pmc8380_5_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmc8380_6_die_temp: channel@603 {
+ reg = <ADC5_GEN3_DIE_TEMP(6)>;
+ label = "pmc8380_6_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@803 {
+ reg = <ADC5_GEN3_DIE_TEMP(8)>;
+ label = "pm8550ve_8_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@903 {
+ reg = <ADC5_GEN3_DIE_TEMP(9)>;
+ label = "pm8550ve_9_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
};
/* PMC8380C */
@@ -291,6 +421,8 @@ pm8550_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>;
+ io-channel-names = "thermal";
};
pm8550_gpios: gpio@8800 {
@@ -301,6 +433,18 @@ pm8550_gpios: gpio@8800 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+ sys_therm_0_gpio3: sys-therm-0-gpio3-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-high-impedance;
+ };
+
+ sys_therm_1_gpio4: sys-therm-1-gpio4-state {
+ pins = "gpio4";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-high-impedance;
+ };
};
pm8550_flash: led-controller@ee00 {
@@ -329,6 +473,8 @@ pm8550ve_2_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>;
+ io-channel-names = "thermal";
};
pm8550ve_2_gpios: gpio@8800 {
@@ -354,6 +500,8 @@ pmc8380_3_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>;
+ io-channel-names = "thermal";
};
pmc8380_3_gpios: gpio@8800 {
@@ -378,6 +526,8 @@ pmc8380_4_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>;
+ io-channel-names = "thermal";
};
pmc8380_4_gpios: gpio@8800 {
@@ -402,6 +552,8 @@ pmc8380_5_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(5)>;
+ io-channel-names = "thermal";
};
pmc8380_5_gpios: gpio@8800 {
@@ -426,6 +578,8 @@ pmc8380_6_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>;
+ io-channel-names = "thermal";
};
pmc8380_6_gpios: gpio@8800 {
@@ -451,6 +605,8 @@ pm8550ve_8_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(8)>;
+ io-channel-names = "thermal";
};
pm8550ve_8_gpios: gpio@8800 {
@@ -476,6 +632,8 @@ pm8550ve_9_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(9)>;
+ io-channel-names = "thermal";
};
pm8550ve_9_gpios: gpio@8800 {
diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi
index 394e65518ac5..661dca4fbee3 100644
--- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi
@@ -10,6 +10,7 @@
/delete-node/ &pmc8380_6;
/delete-node/ &pmc8380_6_thermal;
+/delete-node/ &pmc8380_6_die_temp;
/ {
reserved-memory {
diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts
index 63e29d2cc4ab..c754104adac7 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts
+++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts
@@ -11,6 +11,7 @@
/delete-node/ &pmc8380_6;
/delete-node/ &pmc8380_6_thermal;
+/delete-node/ &pmc8380_6_die_temp;
/ {
model = "ASUS Vivobook S 15 X1P-42-100";
diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi
index 7f5860d2b6cc..b5226c1ae370 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi
@@ -11,6 +11,7 @@
/delete-node/ &pmc8380_6;
/delete-node/ &pmc8380_6_thermal;
+/delete-node/ &pmc8380_6_die_temp;
/ {
wcn6855-pmu {
diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
index 7ed4116b9590..5de91bca3fd5 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
@@ -10,6 +10,7 @@
/delete-node/ &pmc8380_6;
/delete-node/ &pmc8380_6_thermal;
+/delete-node/ &pmc8380_6_die_temp;
/ {
model = "Qualcomm Technologies, Inc. X1P42100 CRD";
diff --git a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts
index 0f338e457abd..0e4dfb0f0a2a 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts
+++ b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts
@@ -7,6 +7,7 @@
#include "x1-hp-omnibook-x14.dtsi"
/delete-node/ &pmc8380_6;
/delete-node/ &pmc8380_6_thermal;
+/delete-node/ &pmc8380_6_die_temp;
/ {
model = "HP Omnibook X 14-fe1";
diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
index 500809772097..9e6f679758a9 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
+++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
@@ -18,6 +18,7 @@
/delete-node/ &pmc8380_6;
/delete-node/ &pmc8380_6_thermal;
+/delete-node/ &pmc8380_6_die_temp;
/ {
model = "Lenovo ThinkBook 16 Gen 7 QOY";
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support
2026-07-28 15:49 ` [PATCH v4 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support Jishnu Prakash
@ 2026-07-28 16:29 ` sashiko-bot
0 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-07-28 16:29 UTC (permalink / raw)
To: Jishnu Prakash; +Cc: robh, conor+dt, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Mismatch between configured pinctrl pins and ADC AMUX channels for system thermistors.
--
--- Patch [4]: [PATCH v4 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support ---
commit abcfdfa0b33d2473870045c8d56652b236189ed1
Author: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
arm64: dts: qcom: hamoa-pmics: Add ADC support
This commit adds ADC nodes and defines channels for die temperature, VPH power,
and system thermistors for various PMICs on hamoa boards. It also wires up
io-channels for the temp_alarm nodes to get temperature readings.
> diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
> index 6a31a0adf8be4..17d754d57e189 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
[ ... ]
> @@ -277,6 +279,134 @@ pmk8550_pwm: pwm {
>
> status = "disabled";
> };
> +
> + pmk8550_vadc: adc@9000 {
> + compatible = "qcom,spmi-adc5-gen3";
> + reg = <0x9000>, <0x9100>;
> + interrupts-extended = <&spmi_bus0 0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
> + <&spmi_bus0 0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> + pinctrl-0 = <&sys_therm_0_gpio3>, <&sys_therm_1_gpio4>;
> + pinctrl-names = "default";
[ ... ]
> + channel@14a {
> + reg = <ADC5_GEN3_AMUX1_GPIO_100K_PU(1)>;
> + label = "pm8550_gpio_01";
> + qcom,ratiometric;
> + qcom,hw-settle-time = <200>;
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + channel@14b {
> + reg = <ADC5_GEN3_AMUX2_GPIO_100K_PU(1)>;
> + label = "pm8550_gpio_02";
> + qcom,ratiometric;
> + qcom,hw-settle-time = <200>;
> + qcom,pre-scaling = <1 1>;
> + };
[Severity: Medium]
Is there a mismatch between the configured pinctrl pins and the ADC AMUX
channels being read here?
The pinctrl explicitly configures GPIO3 and GPIO4 (sys_therm_0_gpio3 and
sys_therm_1_gpio4) as analog inputs for the system thermistors. However, the
channel definitions above use ADC5_GEN3_AMUX1_GPIO (GPIO1) and
ADC5_GEN3_AMUX2_GPIO (GPIO2) with labels pm8550_gpio_01 and pm8550_gpio_02.
Could this cause the ADC to read from unconfigured pins and return floating
temperature values, while the actual thermistor pins remain unread?
[ ... ]
> @@ -301,6 +433,18 @@ pm8550_gpios: gpio@8800 {
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> +
> + sys_therm_0_gpio3: sys-therm-0-gpio3-state {
> + pins = "gpio3";
> + function = PMIC_GPIO_FUNC_NORMAL;
> + bias-high-impedance;
> + };
> +
> + sys_therm_1_gpio4: sys-therm-1-gpio4-state {
> + pins = "gpio4";
> + function = PMIC_GPIO_FUNC_NORMAL;
> + bias-high-impedance;
> + };
> };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260728-adc5_gen3_dt-v4-0-355f0edece77@oss.qualcomm.com?part=4
^ permalink raw reply [flat|nested] 8+ messages in thread