Re: [PATCH v8 3/6] arm64: dts: qcom: Add device tree for Nord Embedded variant

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Pin multiplexing conflicts due to copy-paste errors in QUP serial engine pinctrl definitions.
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--- Patch [3]: [PATCH v8 3/6] arm64: dts: qcom: Add device tree for Nord Embedded variant ---
commit bf3ea50b3b635e297d8a3608bd66c8e13734144c
Author: Shawn Guo <shengchao.guo@oss.qualcomm.com>

arm64: dts: qcom: Add device tree for Nord Embedded variant

This commit adds a new device tree file for the Nord Embedded variant. It
defines platform resources like clocks, regulators, and pin control
configurations. It also describes how they wire up with existing components.

> diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> new file mode 100644
> index 0000000000000..032d384f6eb3e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi

[ ... ]

> +	qup_uart0_default: qup-uart0-default-state {
> +		pins = "gpio109", "gpio110";
> +		function = "qup0_se0";
> +		drive-strength = <2>;
> +		bias-disable;
> +	};
> +
> +	qup_uart1_default: qup-uart1-default-state {
> +		pins = "gpio109", "gpio110";
> +		function = "qup0_se1";

[Severity: Medium]
Does this code assign the same pins (gpio109, gpio110) to both SE0 and SE1?
If both are enabled, it looks like this will cause a pin control conflict
during driver probe.

[ ... ]

> +	qup_uart5_default: qup-uart5-default-state {
> +		pins = "gpio109", "gpio110";
> +		function = "qup0_se5";

[Severity: Medium]
Are gpio109 and gpio110 meant to be used for SE5 here? They appear to be
reused again from the SE0 and SE1 pin configurations above, which might lead
to a conflict.

[ ... ]

> +	qup_uart15_default: qup-uart15-default-state {
> +		pins = "gpio143", "gpio144";
> +		function = "qup2_se1";
> +		drive-strength = <2>;
> +		bias-disable;
> +	};

[ ... ]

> +	qup_uart18_default: qup-uart18-default-state {
> +		pins = "gpio143", "gpio144";
> +		function = "qup2_se4";

[Severity: Medium]
Is it intentional to reuse gpio143 and gpio144 for SE18? These same pins
were assigned to SE15 in qup_uart15_default, which could cause another
hardware mapping conflict.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260729010022.875799-1-shengchao.guo@oss.qualcomm.com?part=3