Re: [PATCH v6 3/3] arm64: dts: qcom: eliza-evk: Add PCIe1 with TC9563 PCIe switch

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Endpoint devices incorrectly define PCI bridge properties (`device_type = "pci"`, `ranges`, etc.).
- [Low] The comment explaining that PERST# and RESX# share the same GPIO is misplaced, causing confusion about pin assignments.
--

--- Patch [3]: [PATCH v6 3/3] arm64: dts: qcom: eliza-evk: Add PCIe1 with TC9563 PCIe switch ---
commit 86f389de1416cf57b1a057c5cc8316c6fc164073
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: eliza-evk: Add PCIe1 with TC9563 PCIe switch

The Eliza EVK board connects PCIe1 (8GT/s x2) to a Toshiba TC9563 PCIe
switch. Enable PCIe1, QMP PHY nodes, and TC9563 nodes on I2C and PCIe.

> diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi
> index b35fffb509765..419e737c54e6f 100644
> --- a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi
> +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi
[ ... ]
> +&pcie1_port0 {
> +	wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
> +	/* Same GPIO is used for both PERST# and resx-gpio */

[Severity: Low]
Is this comment placed correctly?

The comment implies that wake-gpios (TLMM 53) is the shared reset GPIO, but
resx-gpios is defined as TLMM 54 further down in the tc9563 node. Should this
comment be moved above resx-gpios or the omitted reset-gpios property to avoid
confusion?

> +
> +	tc9563: pcie@0,0 {
> +		compatible = "pci1179,0623";
> +		reg = <0x10000 0x0 0x0 0x0 0x0>;
[ ... ]
> +		pcie@3,0 {
> +			reg = <0x21800 0x0 0x0 0x0 0x0>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			device_type = "pci";
> +			ranges;
> +			bus-range = <0x5 0xff>;
> +
> +			pcie@0,0 {
> +				reg = <0x50000 0x0 0x0 0x0 0x0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				device_type = "pci";
> +				ranges;
> +			};
> +
> +			pcie@0,1 {
> +				reg = <0x50100 0x0 0x0 0x0 0x0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				device_type = "pci";
> +				ranges;
> +			};

[Severity: Medium]
Are pcie@0,0 and pcie@0,1 leaf endpoints?

If these child nodes represent leaf endpoints (like Ethernet MAC devices), they
should not include properties strictly reserved for PCI-to-PCI bridges or Root
Ports such as #address-cells, #size-cells, ranges, or device_type = "pci".

Will this cause dtbs_check validation errors or cause the OF/PCI subsystem to
misinterpret these leaf nodes as PCI bridges?

> +		};
> +	};
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260730-eliza_evk-v6-0-40ece2d33114@oss.qualcomm.com?part=3