From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-pm@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Subject: Re: [PATCH v6 2/3] arm64: dts: qcom: eliza-evk: Add PCIe0 with M.2 E key connector
Date: Thu, 30 Jul 2026 11:53:47 +0530 [thread overview]
Message-ID: <8cb3869b-98e1-4631-952c-2106986527cb@oss.qualcomm.com> (raw)
In-Reply-To: <vatryeq6qsan342wow42rosabjofi6cqkom7aczllko4kw7n4t@v7k3fxat7nfi>
On 7/30/2026 10:38 AM, Manivannan Sadhasivam wrote:
> On Thu, Jul 30, 2026 at 10:18:54AM +0530, Krishna Chaitanya Chundru wrote:
>> The Eliza EVK board features an M.2 E key connector connected to PCIe0.
>> Enable the PCIe0 root port and its QMP PHY with the necessary RPMH
>> regulator supplies. The M.2 slot's 3.3V supply rail is GPIO-controlled
>> via a TCA9538 I/O expander on I2C4.
>>
>> The M.2 E key slot hosts a WLAN card connected over PCIe and a Bluetooth
>> device connected over UART. Model the connector using the
>> pcie-m2-e-connector binding, wiring the PCIe root port and UART5 for
>> the respective interfaces.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
>> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/eliza-evk.dtsi | 116 ++++++++++++++++++++++++++++++++
>> 1 file changed, 116 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi
>> index e47b24f8b827..b35fffb50976 100644
>> --- a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi
>> @@ -11,6 +11,92 @@ aliases {
>> chosen {
>> stdout-path = "serial0:115200n8";
>> };
>> +
>> + vreg_pcie_m_3p3: regulator-3p3 {
>> + compatible = "regulator-fixed";
>> +
>> + regulator-name = "vreg_3p3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> +
>> + gpio = <&gpio_expander1 6 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + };
>> +
>> + connector-0 {
>> + compatible = "pcie-m2-e-connector";
>> + vpcie3v3-supply = <&vreg_pcie_m_3p3>;
>> + w-disable1-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
>> + w-disable2-gpios = <&pm8550vs_g_gpios 4 GPIO_ACTIVE_HIGH>;
> Hmm, Sashiko pointed out the polarity issue here, GPIO_ACTIVE_HIGH. Is it a
> mistake?
No it is working with active high only, it is how they connected in the HW.
- Krishna Chaitanya.
> - Mani
>
>> +
>> + pinctrl-0 = <&m2_w_disable1>, <&m2_w_disable2>;
>> + pinctrl-names = "default";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + m2_e_pcie_ep: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&pcieport0_ep>;
>> + };
>> + };
>> +
>> + port@3 {
>> + reg = <3>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + m2_e_uart_ep: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&uart5_ep>;
>> + };
>> + };
>> + };
>> + };
>> +};
>> +
>> +&i2c4 {
>> + pinctrl-0 = <&qup_i2c4_data_clk>;
>> + pinctrl-names = "default";
>> +
>> + clock-frequency = <400000>;
>> +
>> + status = "okay";
>> +
>> + gpio_expander1: gpio@3c {
>> + compatible = "ti,tca9538";
>> + #gpio-cells = <2>;
>> + gpio-controller;
>> + reg = <0x3c>;
>> + };
>> +};
>> +
>> +&pcie0 {
>> + status = "okay";
>> +};
>> +
>> +&pcie0_phy {
>> + vdda-phy-supply = <&vreg_l1k>;
>> + vdda-pll-supply = <&vreg_l3k>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&pcie0_port0 {
>> + wake-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
>> + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
>> +
>> + port {
>> + pcieport0_ep: endpoint {
>> + remote-endpoint = <&m2_e_pcie_ep>;
>> + };
>> + };
>> };
>>
>> &uart13 {
>> @@ -18,3 +104,33 @@ &uart13 {
>>
>> status = "okay";
>> };
>> +
>> +&uart5 {
>> + status = "okay";
>> +
>> + port {
>> + uart5_ep: endpoint {
>> + remote-endpoint = <&m2_e_uart_ep>;
>> + };
>> + };
>> +};
>> +
>> +&pm8550vs_g_gpios {
>> + m2_w_disable2: m2-w-disable2-state {
>> + pins = "gpio4";
>> + function = "normal";
>> + input-disable;
>> + output-enable;
>> + bias-disable;
>> + power-source = <2>;
>> + };
>> +};
>> +
>> +&tlmm {
>> + m2_w_disable1: m2-w-disable1-state {
>> + pins = "gpio35";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> +};
>>
>> --
>> 2.34.1
>>
next prev parent reply other threads:[~2026-07-30 6:23 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-30 4:48 [PATCH v6 0/3] arm64: dts: qcom: eliza-evk: Enable PCIe0 and PCIe1 with M.2 and TC9563 switch Krishna Chaitanya Chundru
2026-07-30 4:48 ` [PATCH v6 1/3] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes Krishna Chaitanya Chundru
2026-07-30 5:18 ` sashiko-bot
2026-07-30 7:54 ` Manivannan Sadhasivam
2026-07-30 4:48 ` [PATCH v6 2/3] arm64: dts: qcom: eliza-evk: Add PCIe0 with M.2 E key connector Krishna Chaitanya Chundru
2026-07-30 5:06 ` sashiko-bot
2026-07-30 5:08 ` Manivannan Sadhasivam
2026-07-30 6:23 ` Krishna Chaitanya Chundru [this message]
2026-07-30 4:48 ` [PATCH v6 3/3] arm64: dts: qcom: eliza-evk: Add PCIe1 with TC9563 PCIe switch Krishna Chaitanya Chundru
2026-07-30 5:10 ` sashiko-bot
2026-07-30 5:25 ` Manivannan Sadhasivam
2026-07-30 7:42 ` Konrad Dybcio
2026-07-30 7:52 ` Manivannan Sadhasivam
2026-07-30 7:59 ` Konrad Dybcio
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