[PATCH 0/6] sunxi: net: add Ethernet support for X96QPro+

[PATCH 0/6] sunxi: net: add Ethernet support for X96QPro+

[Andre Przywara]

The X96QPro+ is a TV box with an Allwinner H728 SoC (the same die as the
Allwinner A523). The Ethernet connection is using the secondary GMAC,
connected to a MAXIO MAE0621A-Q2C PHY. The setup is a bit special, as it's
not using a crystal oscillator to clock the PHY, but instead a clock
fanout pin from the SoC.
To make Ethernet work on this device, we need this clock, we need to
adjust the PHY-ID, and we need the devicetree bits:

- To make the PHY operational, the PHY driver needs to enable the fanout
clock. The generic PHY DT binding describes such a clock already, so
the binding needs no addition in this respect, but it's in each PHY
driver's responsibility to take care of that clock enablement, which
is done in the first two patches.

- Also the MAXIO PHY used on the board is the -Q2C variant, which uses a
slightly different PHY-ID than the Q3C variant described in the current
version of the driver. Add this new PHY-ID to the driver, but also
allow it in the DT binding, since we need to use that PHY-ID compatible
string version, to skip the MDIO probing process, which wouldn't work
without the clock. This is done in patches 3 and 4.

- Lastly we need to describe the config in the board's devicetree. Patch
5 adds clock fanout pins to the .dtsi, which the final patch 6 enables
the MAC and PHY nodes and connects them together.

This enables the box' Ethernet functionality, made possible by the new
MAXIO PHY driver. The MAC part is already supported for a few releases.

This is based on v7.2-rc1, plus version 2 of the MAXIO PHY driver as
sent by Liu Changjie. Since those two patches have been reviewed already
some weeks back, I assume they are ready to go. Please let me know if
that is not the case and if I can help with anything there.

Cheers,
Andre


Andre Przywara (6):
  net: phy: maxio: prepare for more DT properties
  net: phy: maxio: parse and enable PHY clock from generic DT binding
  dt-bindings: net: Maxio PHY: add PHY-ID for -Q2C variant
  net: phy: maxio: extend PHY ID matching
  arm64: dts: allwinner: a523: add EPHY 25MHz clock fanout pins
  arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support

 .../bindings/net/maxio,mae0621a.yaml          |  4 ++-
 .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 14 ++++++++++
 .../dts/allwinner/sun55i-h728-x96qpro+.dts    | 28 +++++++++++++++++++
 drivers/net/phy/maxio.c                       | 27 +++++++++++-------
 4 files changed, 62 insertions(+), 11 deletions(-)


base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
prerequisite-patch-id: aa3058cd68d68f361088b39cac0b12fb96be8b55
prerequisite-patch-id: 90f19ec9993e373e39efda42984c88d7b51151e5
-- 
2.43.0

[PATCH 1/6] net: phy: maxio: prepare for more DT properties

[Andre Przywara]

The probe routine for the Maxio PHY returns early if the optional
maxio,clk-out-frequency-hz property is not found. That prevents looking
for other properties.

Refactor the routine to handle the property in an if-clause, to allow
more actions in the probe routine later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/net/phy/maxio.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/net/phy/maxio.c b/drivers/net/phy/maxio.c
index d2cb23895646..95a2169f25df 100644
--- a/drivers/net/phy/maxio.c
+++ b/drivers/net/phy/maxio.c
@@ -43,18 +43,18 @@ static int maxio_mae0621a_probe(struct phy_device *phydev)
 
 	ret = device_property_read_u32(dev, "maxio,clk-out-frequency-hz",
 				       &frequency);
-	if (ret == -EINVAL)
-		return 0;
-	if (ret)
+	if (!ret) {
+		if (frequency != 125000000) {
+			phydev_err(phydev, "invalid CLKOUT frequency %u\n",
+				   frequency);
+			return -EINVAL;
+		}
+
+		priv->clk_out_125m = true;
+	} else if (ret != -EINVAL) {
 		return ret;
-
-	if (frequency != 125000000) {
-		phydev_err(phydev, "invalid CLKOUT frequency %u\n", frequency);
-		return -EINVAL;
 	}
 
-	priv->clk_out_125m = true;
-
 	return 0;
 }
 
-- 
2.43.0

[PATCH 2/6] net: phy: maxio: parse and enable PHY clock from generic DT binding

[Andre Przywara]

The generic PHY DT binding features a clocks property, which describes
the clock input to the PHY. Typically this is a crystal oscillator, so
it works without software interaction. But some boards want to save some
pennies on that part, and let a clock fanout pin from the SoC provide this
clock signal. In this case the PHY probe routine needs to enable this
clock explicitly.

Look for a "clocks" property inside the PHY node and enable that clock,
if one is provided.

This allows boards with a SoC-driven PHY clock to use the PHY. Please
note that without the clock enabled, the PHY will not be detected on the
MDIO bus, so the PHY-ID needs to be explicitly named in the PHY
compatible string:
	compatible = "ethernet-phy-id7b74.4411";

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/net/phy/maxio.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/net/phy/maxio.c b/drivers/net/phy/maxio.c
index 95a2169f25df..5fabf99fb90f 100644
--- a/drivers/net/phy/maxio.c
+++ b/drivers/net/phy/maxio.c
@@ -2,6 +2,7 @@
 /* Driver for Maxio Ethernet PHYs. */
 
 #include <linux/bitops.h>
+#include <linux/clk.h>
 #include <linux/module.h>
 #include <linux/phy.h>
 #include <linux/property.h>
@@ -15,6 +16,7 @@
 #define MAXIO_MAE0621A_CLKOUT_ENABLE	BIT(0)
 
 struct maxio_priv {
+	struct clk *clk;
 	bool clk_out_125m;
 };
 
@@ -55,6 +57,11 @@ static int maxio_mae0621a_probe(struct phy_device *phydev)
 		return ret;
 	}
 
+	/* PHY clock from the generic PHY binding */
+	priv->clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, NULL);
+	if (IS_ERR(priv->clk))
+		return PTR_ERR(priv->clk);
+
 	return 0;
 }
 
-- 
2.43.0

[PATCH 3/6] dt-bindings: net: Maxio PHY: add PHY-ID for -Q2C variant

[Andre Przywara]

The Maxio MAE0621A PHY is out there in at least two variants: the
MAE0621A-Q3C chip, with the PHY-ID 0x7b744412, and the -Q2C variant,
identifying as 0x7b744411.

Allow both IDs to be used as the PHY compatible string, to potentially
avoid probing, which might fail due to unavailable resources (clock).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 Documentation/devicetree/bindings/net/maxio,mae0621a.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/maxio,mae0621a.yaml b/Documentation/devicetree/bindings/net/maxio,mae0621a.yaml
index f1ea54583225..c4d06c626168 100644
--- a/Documentation/devicetree/bindings/net/maxio,mae0621a.yaml
+++ b/Documentation/devicetree/bindings/net/maxio,mae0621a.yaml
@@ -14,7 +14,9 @@ allOf:
 
 properties:
   compatible:
-    const: ethernet-phy-id7b74.4412
+    enum:
+      - ethernet-phy-id7b74.4411
+      - ethernet-phy-id7b74.4412
 
   maxio,clk-out-frequency-hz:
     description:
-- 
2.43.0

[PATCH 4/6] net: phy: maxio: extend PHY ID matching

[Andre Przywara]

Currently the maxio Ethernet PHY driver expects a PHY matching exactly the
one ID provided: 0x7b744412. The Maxio MAE0621A-Q3C model used on
the Allwinner based X96QPro+ TV box uses a slightly different PHY ID:
0x7b744411.

Replace the "exact match" requirement with the more relaxed "model
match" version, which ignores the lowest 4 bits of the PHY ID. Both
PHYs should now be recognised by the driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/net/phy/maxio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/maxio.c b/drivers/net/phy/maxio.c
index 5fabf99fb90f..d97fb50cdbe1 100644
--- a/drivers/net/phy/maxio.c
+++ b/drivers/net/phy/maxio.c
@@ -87,7 +87,7 @@ static int maxio_mae0621a_config_init(struct phy_device *phydev)
 
 static struct phy_driver maxio_drivers[] = {
 	{
-		PHY_ID_MATCH_EXACT(MAXIO_MAE0621A_PHY_ID),
+		PHY_ID_MATCH_MODEL(MAXIO_MAE0621A_PHY_ID),
 		.name		= "Maxio MAE0621A",
 		.probe		= maxio_mae0621a_probe,
 		.config_init	= maxio_mae0621a_config_init,
@@ -100,7 +100,7 @@ static struct phy_driver maxio_drivers[] = {
 module_phy_driver(maxio_drivers);
 
 static const struct mdio_device_id __maybe_unused maxio_tbl[] = {
-	{ PHY_ID_MATCH_EXACT(MAXIO_MAE0621A_PHY_ID) },
+	{ PHY_ID_MATCH_MODEL(MAXIO_MAE0621A_PHY_ID) },
 	{ }
 };
 MODULE_DEVICE_TABLE(mdio, maxio_tbl);
-- 
2.43.0

[PATCH 5/6] arm64: dts: allwinner: a523: add EPHY 25MHz clock fanout pins

[Andre Przywara]

The Allwinner A523 SoC family provides two clock fanout pins, which are
backed by gated clocks fixed to 25 MHz, divided down from the main
peripheral PLL. Those are meant to clock an Ethernet PHY, and allow to
save an external crystal oscillator typically employed for that purpose.

Add the pin descriptions of the two pins for those clocks, one is within
the RGMII0 pins, the other within the RGMII1 pins, although the clock
fanout works completely independently from the two MACs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index ca6a16807049..1a95c0a21509 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -147,6 +147,20 @@ pio: pinctrl@2000000 {
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			/omit-if-no-ref/
+			ephy0_25m_pin: ephy0-25m-pin {
+				pins = "PH13";
+				allwinner,pinmux = <5>;
+				function = "ephy_25m";
+			};
+
+			/omit-if-no-ref/
+			ephy1_25m_pin: ephy1-25m-pin {
+				pins = "PJ10";
+				allwinner,pinmux = <5>;
+				function = "ephy_25m";
+			};
+
 			/omit-if-no-ref/
 			i2s2_pi_pins: i2s2-pi-pins {
 				pins = "PI2", "PI3", "PI4", "PI5";
-- 
2.43.0

[PATCH 6/6] arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support

[Andre Przywara]

The X96QPro+ TV Box features a Gigabit Ethernet capable port, which is
driven by the secondary EMAC, and supported by a Maxio MAE0621A PHY.

Add the required devicetree nodes to enable that port.

The PHY is not clocked by an external crystal oscillator, but relies on a
SoC-provided clock fanout pin for its 25 MHz reference input clock. The
clock is referenced in the PHY DT node, which not all systems might enable
before scanning the MDIO bus. To help with that problem, the PHY compatible
string is using the PHY ID, which means the MDIO bus scanning can be
skipped.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../dts/allwinner/sun55i-h728-x96qpro+.dts    | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
index a96927fbdadd..568a4fae84df 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
@@ -13,6 +13,7 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &gmac1;
 	};
 
 	chosen {
@@ -54,11 +55,38 @@ &ehci1 {
 	status = "okay";
 };
 
+&gmac1 {
+	clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii1_pins>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ext_rgmii_phy>;
+	phy-supply = <&reg_cldo3>;
+
+	tx-internal-delay-ps = <200>;
+	rx-internal-delay-ps = <500>;
+
+	status = "okay";
+};
+
 &gpu {
 	mali-supply = <&reg_dcdc2>;
 	status = "okay";
 };
 
+&mdio1 {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-id7b74.4411";
+		reg = <1>;
+		clocks = <&ccu CLK_EMAC1_25M>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ephy_25m_pin>;
+		reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <150000>;
+	};
+};
+
 &mmc0 {
 	vmmc-supply = <&reg_vcc3v3>;
 	cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */
-- 
2.43.0

Re: [PATCH 4/6] net: phy: maxio: extend PHY ID matching

[Per Larsson]

On Mon,  3 Aug 2026 12:14:50 +0200
Andre Przywara <andre.przywara@arm.com> wrote:

> Currently the maxio Ethernet PHY driver expects a PHY matching
> exactly the one ID provided: 0x7b744412. The Maxio MAE0621A-Q3C model
> used on the Allwinner based X96QPro+ TV box uses a slightly different
> PHY ID: 0x7b744411.

A somewhat unfortunate typo here claims that the TV box has the -Q3C
variant when it in reality has the -Q2C variant (Cover letter and other
pathches in the series gets it right).

Re: [PATCH 1/6] net: phy: maxio: prepare for more DT properties

[Andrew Lunn]

On Mon, Aug 03, 2026 at 12:14:47PM +0200, Andre Przywara wrote:
> The probe routine for the Maxio PHY returns early if the optional
> maxio,clk-out-frequency-hz property is not found. That prevents looking
> for other properties.
> 
> Refactor the routine to handle the property in an if-clause, to allow
> more actions in the probe routine later.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  drivers/net/phy/maxio.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/net/phy/maxio.c b/drivers/net/phy/maxio.c
> index d2cb23895646..95a2169f25df 100644
> --- a/drivers/net/phy/maxio.c
> +++ b/drivers/net/phy/maxio.c
> @@ -43,18 +43,18 @@ static int maxio_mae0621a_probe(struct phy_device *phydev)
>  
>  	ret = device_property_read_u32(dev, "maxio,clk-out-frequency-hz",
>  				       &frequency);
> -	if (ret == -EINVAL)
> -		return 0;
> -	if (ret)
> +	if (!ret) {
> +		if (frequency != 125000000) {
> +			phydev_err(phydev, "invalid CLKOUT frequency %u\n",
> +				   frequency);
> +			return -EINVAL;
> +		}
> +
> +		priv->clk_out_125m = true;
> +	} else if (ret != -EINVAL) {
>  		return ret;

The normal pattern is to check for errors and return them. So i would
do this test first.

 	ret = device_property_read_u32(dev, "maxio,clk-out-frequency-hz",
  				       &frequency);
        if (ret) {
	   if (ret != -EINVAL)
	        return ret;
	} else {
		if (frequency != 125000000) {
			phydev_err(phydev, "invalid CLKOUT frequency %u\n",
				   frequency);
			return -EINVAL;
		}

		priv->clk_out_125m = true;
        }


	Andrew

Re: [PATCH 2/6] net: phy: maxio: parse and enable PHY clock from generic DT binding

[Andrew Lunn]

On Mon, Aug 03, 2026 at 12:14:48PM +0200, Andre Przywara wrote:
> The generic PHY DT binding features a clocks property, which describes
> the clock input to the PHY. Typically this is a crystal oscillator, so
> it works without software interaction. But some boards want to save some
> pennies on that part, and let a clock fanout pin from the SoC provide this
> clock signal. In this case the PHY probe routine needs to enable this
> clock explicitly.
> 
> Look for a "clocks" property inside the PHY node and enable that clock,
> if one is provided.
> 
> This allows boards with a SoC-driven PHY clock to use the PHY. Please
> note that without the clock enabled, the PHY will not be detected on the
> MDIO bus, so the PHY-ID needs to be explicitly named in the PHY
> compatible string:
> 	compatible = "ethernet-phy-id7b74.4411";
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 4/6] net: phy: maxio: extend PHY ID matching

[Andrew Lunn]

On Mon, Aug 03, 2026 at 12:14:50PM +0200, Andre Przywara wrote:
> Currently the maxio Ethernet PHY driver expects a PHY matching exactly the
> one ID provided: 0x7b744412. The Maxio MAE0621A-Q3C model used on
> the Allwinner based X96QPro+ TV box uses a slightly different PHY ID:
> 0x7b744411.
> 
> Replace the "exact match" requirement with the more relaxed "model
> match" version, which ignores the lowest 4 bits of the PHY ID. Both
> PHYs should now be recognised by the driver.

Is there any documentation to suggest this is different versions of
the same PHY? The datasheet sometimes document the lower nibble as
being version.

	Andrew

Re: [PATCH 6/6] arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support

[Andrew Lunn]

> +&gmac1 {
> +	clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&rgmii1_pins>;
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ext_rgmii_phy>;
> +	phy-supply = <&reg_cldo3>;
> +
> +	tx-internal-delay-ps = <200>;
> +	rx-internal-delay-ps = <500>;

500ns is quite big. How did you come to this value? Do you have the
schematic & gerber files? Does the lines look unbalanced?

	Andrew

Re: [PATCH 6/6] arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support

[Chen-Yu Tsai]

On Tue, Aug 4, 2026 at 10:53 AM Andrew Lunn <andrew@lunn.ch> wrote:
>
> > +&gmac1 {
> > +     clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&rgmii1_pins>;
> > +     phy-mode = "rgmii-id";
> > +     phy-handle = <&ext_rgmii_phy>;
> > +     phy-supply = <&reg_cldo3>;
> > +
> > +     tx-internal-delay-ps = <200>;
> > +     rx-internal-delay-ps = <500>;
>
> 500ns is quite big. How did you come to this value? Do you have the
> schematic & gerber files? Does the lines look unbalanced?

Unit is ps, not ns.


ChenYu

Re: [PATCH 6/6] arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support

[Andrew Lunn]

On Tue, Aug 04, 2026 at 11:11:04AM +0800, Chen-Yu Tsai wrote:
> On Tue, Aug 4, 2026 at 10:53 AM Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > > +&gmac1 {
> > > +     clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;
> > > +     pinctrl-names = "default";
> > > +     pinctrl-0 = <&rgmii1_pins>;
> > > +     phy-mode = "rgmii-id";
> > > +     phy-handle = <&ext_rgmii_phy>;
> > > +     phy-supply = <&reg_cldo3>;
> > > +
> > > +     tx-internal-delay-ps = <200>;
> > > +     rx-internal-delay-ps = <500>;
> >
> > 500ns is quite big. How did you come to this value? Do you have the
> > schematic & gerber files? Does the lines look unbalanced?
> 
> Unit is ps, not ns.

Yes, sorry, wrong units. But still 500ps is very big. You have the PHY
adding 2ns, due to rgmii-id, and you add another 500ps?

       Andrew