[PATCH v2] arm64: dts: ti: k3-am64: Enable IO expander interrupt

[PATCH v2] arm64: dts: ti: k3-am64: Enable IO expander interrupt

[Judith Mendez]

On AM64 EVM and SK boards, MMC1_SDWP is used for IO expander interrupt,
remove from MMC1 pinmux node and setup as exp1 IO expander interrupt.

Signed-off-by: Judith Mendez <jm@ti.com>
---
Change from v1:
- Add header files
- Change IRQ_TYPE_LEVEL_HIGH to IRQ_TYPE_EDGE_FALLING

V1 is from the original patch series here:
Link: https://lore.kernel.org/linux-devicetree/20260729195958.671147-1-jm@ti.com/
---
 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 15 ++++++++++++++-
 arch/arm64/boot/dts/ti/k3-am642-sk.dts  | 15 ++++++++++++++-
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index bc4347cf71140..28fbaf134af4f 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -8,6 +8,7 @@
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/net/ti-dp83867.h>
 #include "k3-am642.dtsi"
 
@@ -259,11 +260,17 @@ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
 			AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
 			AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
 			AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
-			AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
 			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
 		>;
 	};
 
+	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x029c, PIN_INPUT, 7) /* (C20) MMC1_SDWP.GPIO1_78 */
+		>;
+		bootph-all;
+	};
+
 	main_uart1_pins_default: main-uart1-default-pins {
 		pinctrl-single,pins = <
 			AM64X_IOPAD(0x0248, PIN_INPUT, 0)		/* (D16) UART1_CTSn */
@@ -481,6 +488,12 @@ exp1: gpio@22 {
 		bootph-all;
 		compatible = "ti,tca6424";
 		reg = <0x22>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
+		interrupt-parent = <&main_gpio1>;
+		interrupts = <78 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index d28a38c87f32a..aa87845d77598 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/net/ti-dp83867.h>
 #include <dt-bindings/leds/common.h>
 #include "k3-am642.dtsi"
@@ -198,7 +199,6 @@ &main_pmx0 {
 	main_mmc1_pins_default: main-mmc1-default-pins {
 		bootph-all;
 		pinctrl-single,pins = <
-			AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
 			AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
 			AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
 			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
@@ -210,6 +210,13 @@ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
 		>;
 	};
 
+	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x029c, PIN_INPUT, 7) /* (C20) MMC1_SDWP.GPIO1_78 */
+		>;
+		bootph-all;
+	};
+
 	main_uart0_pins_default: main-uart0-default-pins {
 		bootph-all;
 		pinctrl-single,pins = <
@@ -383,6 +390,12 @@ exp1: gpio@70 {
 		bootph-all;
 		compatible = "nxp,pca9538";
 		reg = <0x70>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
+		interrupt-parent = <&main_gpio1>;
+		interrupts = <78 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
-- 
2.54.0

Re: [PATCH v2] arm64: dts: ti: k3-am64: Enable IO expander interrupt

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Configuring a level-sensitive IO expander interrupt as edge-triggered creates a race condition that can permanently drop interrupts.
- [Medium] The internal pull-up is disabled for the open-drain IO expander interrupt line, potentially causing the pin to float if no external pull-up is present.
- [Low] The IO expander node has `bootph-all` but its new `interrupt-parent` (`main_gpio1`) does not, leading to a dangling phandle in the bootloader's DTB.
--

--- Patch [1]: [PATCH v2] arm64: dts: ti: k3-am64: Enable IO expander interrupt ---
commit 17dd1ed4722bb7802cfb997027eb263adde31a41
Author: Judith Mendez <jm@ti.com>

arm64: dts: ti: k3-am64: Enable IO expander interrupt

On AM64 EVM and SK boards, MMC1_SDWP is used for IO expander interrupt,
remove from MMC1 pinmux node and setup as exp1 IO expander interrupt.

Link: https://lore.kernel.org/linux-devicetree/20260729195958.671147-1-jm@ti.com/

> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
[ ... ]
> @@ -481,6 +488,12 @@ exp1: gpio@22 {
>  		bootph-all;
>  		compatible = "ti,tca6424";
>  		reg = <0x22>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
> +		interrupt-parent = <&main_gpio1>;

[Severity: Low]
Does this create a dangling phandle in the bootloader's DTB?

The exp1 node contains the bootph-all property, meaning U-Boot's fdtgrep
tool will extract it into the SPL device tree. However, it seems the
main_gpio1 node lacks the bootph-all property and will be stripped out of
the SPL DTB, leaving this interrupt-parent pointing to a missing node.

> +		interrupts = <78 IRQ_TYPE_EDGE_FALLING>;

[Severity: High]
Could configuring this as an edge-triggered interrupt cause a race condition
that permanently stalls the IO expander?

The IO expanders (TCA6424 and PCA9538) generate an active-low, level-sensitive
interrupt that remains asserted (low) as long as unacknowledged events exist.
If an input changes state while an existing interrupt is already being serviced,
the line will remain low.

Because it is edge-triggered here, no subsequent falling edge will be observed,
and since the consumer driver doesn't poll the pending state before returning,
it appears the interrupt controller will miss all future events.

> +		interrupt-controller;
> +		#interrupt-cells = <2>;
>  		gpio-controller;
[ ... ]
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
[ ... ]
> @@ -198,7 +199,6 @@ &main_pmx0 {
>  	main_mmc1_pins_default: main-mmc1-default-pins {
>  		bootph-all;
>  		pinctrl-single,pins = <
> -			AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
[ ... ]
> +	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
> +		pinctrl-single,pins = <
> +			AM64X_IOPAD(0x029c, PIN_INPUT, 7) /* (C20) MMC1_SDWP.GPIO1_78 */

[Severity: Medium]
Will this disabled internal pull-up cause the interrupt line to float?

The IO expanders drive an active-low, open-drain interrupt line which requires
a pull-up. The original configuration explicitly used PIN_INPUT_PULLUP.

By changing this to PIN_INPUT, the internal pull-up is disabled. If the board
does not have a physical external pull-up resistor, the open-drain line could
float and generate spurious falling edges.

> +		>;
> +		bootph-all;
> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260805003859.412474-1-jm@ti.com?part=1