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From: sashiko-bot@kernel.org
To: "Saravanakrishnan Krishnamoorthy" <skrishnamoorthy@rambus.com>
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 16/19] crypto: cmh - add SLH-DSA/LMS/XMSS (HCQ)
Date: Thu, 06 Aug 2026 20:43:35 +0000	[thread overview]
Message-ID: <20260806204335.AE2321F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260806195519.2703224-17-skrishnamoorthy@rambus.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] DMA write-after-free vulnerability on hardware timeout.
- [Medium] Improper rejection of valid 0-length messages for cryptographic operations.
--

--- Patch [16]: [PATCH v3 16/19] crypto: cmh - add SLH-DSA/LMS/XMSS (HCQ) ---
commit 36b1570b3180e707d91edf00a1da1258b01e7320
Author: Alex Ousherovitch <aousherovitch@rambus.com>

crypto: cmh - add SLH-DSA/LMS/XMSS (HCQ)

This commit registers the SLH-DSA, LMS, and XMSS signature algorithms using
the CMH HCQ core. SLH-DSA supports sign and verify operations, while LMS
and XMSS are verify-only.

> diff --git a/drivers/crypto/cmh/cmh_pqc_lms.c b/drivers/crypto/cmh/cmh_pqc_lms.c
> new file mode 100644
> index 0000000000000..3a17ca4786603
> --- /dev/null
> +++ b/drivers/crypto/cmh/cmh_pqc_lms.c
> @@ -0,0 +1,238 @@
> [ ... ]
> +static int cmh_lms_verify(struct crypto_sig *tfm,
> +			  const void *src, unsigned int slen,
> +			  const void *digest, unsigned int dlen)
> +{
> [ ... ]
> +	if (!dlen || dlen > LMS_MAX_MSG_LEN)
> +		return -EINVAL;

[Severity: Medium]
Does this code improperly reject valid 0-length messages? Cryptographic
algorithms natively support empty message inputs, but this check causes them
to fail with -EINVAL.

> +
> +	sig_buf = kmemdup(src, slen, GFP_KERNEL);
> [ ... ]
> +	/* LMS verify traverses Merkle hash chains -- inherently slow */
> +	ret = cmh_tm_submit_sync_tmo(vcq, LMS_VCQ_CMDS, 1, d.mbx_idx,
> +				     cmh_tm_slow_op_timeout_jiffies());
> +
> +out_unmap:
> +	if (!cmh_dma_map_error(pk_dma))
> +		cmh_dma_unmap_single(pk_dma, ctx->pub_key_len, DMA_TO_DEVICE);
> +	if (!cmh_dma_map_error(m_dma))
> +		cmh_dma_unmap_single(m_dma, dlen, DMA_TO_DEVICE);
> +	if (!cmh_dma_map_error(sig_dma))
> +		cmh_dma_unmap_single(sig_dma, slen, DMA_TO_DEVICE);
> +
> +out_free:
> +	kfree(pk_buf);
> +	kfree(m_buf);
> +	kfree(sig_buf);
> +	return ret;
> +}

[Severity: High]
Can this lead to a DMA write-after-free if the hardware times out? If
cmh_tm_submit_sync_tmo() times out and returns -ETIMEDOUT, the caller-owned
heap buffers are unconditionally unmapped and freed. If the hardware later
recovers and completes the transaction, won't it perform an asynchronous DMA
write into memory that has already been returned to the slab allocator?

> diff --git a/drivers/crypto/cmh/cmh_pqc_slhdsa.c b/drivers/crypto/cmh/cmh_pqc_slhdsa.c
> new file mode 100644
> index 0000000000000..4bec4278cd9c6
> --- /dev/null
> +++ b/drivers/crypto/cmh/cmh_pqc_slhdsa.c
> @@ -0,0 +1,377 @@
> [ ... ]
> +static int cmh_slhdsa_sign(struct crypto_sig *tfm,
> +			   const void *src, unsigned int slen,
> +			   void *dst, unsigned int dlen)
> +{
> [ ... ]
> +	if (!slen || slen > SLHDSA_MAX_MSG_LEN)
> +		return -EINVAL;

[Severity: Medium]
Could this explicit rejection of slen == 0 break API conformance? It looks
like it prevents valid empty-message signing requests from being processed.

> +
> +	m_buf = kmemdup(src, slen, GFP_KERNEL);
> [ ... ]
> +	ret = cmh_tm_submit_sync_tmo(vcq, vcq_count, 1, d.mbx_idx,
> +				     cmh_tm_slow_op_timeout_jiffies());
> +
> +	if (!ret) {
> +		/* Sync bounce buffer so CPU sees the DMA-written signature */
> +		cmh_dma_sync_for_cpu(sig_dma, sig_sz, DMA_FROM_DEVICE);
> +		memcpy(dst, sig_buf, sig_sz);
> +		ret = sig_sz;
> +	}
> +
> +out_unmap:
> +	if (sk_buf) {
> +		if (!cmh_dma_map_error(sk_dma))
> +			cmh_dma_unmap_single(sk_dma, sk_sz, DMA_TO_DEVICE);
> +		kfree_sensitive(sk_buf);
> +	}
> +	if (!cmh_dma_map_error(sig_dma))
> +		cmh_dma_unmap_single(sig_dma, sig_sz, DMA_FROM_DEVICE);
> +	if (!cmh_dma_map_error(m_dma))
> +		cmh_dma_unmap_single(m_dma, slen, DMA_TO_DEVICE);
> +
> +out_free:
> +	kfree(sig_buf);
> +	kfree(m_buf);
> +	return ret;
> +}

[Severity: High]
Is it possible for a delayed hardware write to corrupt the heap here? In the
event of a timeout from cmh_tm_submit_sync_tmo(), these DMA buffers are
freed. If the hardware is merely delayed and eventually finishes, it might
write the signature into the now-freed sig_buf.

> [ ... ]
> +static int cmh_slhdsa_verify(struct crypto_sig *tfm,
> +			     const void *src, unsigned int slen,
> +			     const void *digest, unsigned int dlen)
> +{
> [ ... ]
> +	if (!dlen || dlen > SLHDSA_MAX_MSG_LEN)
> +		return -EINVAL;

[Severity: Medium]
Does this code block valid 0-length messages from being verified?

> +
> +	sig_buf = kmemdup(src, slen, GFP_KERNEL);
> [ ... ]
> +	/* SLH-DSA verify recomputes hyper-tree hashes -- inherently slow */
> +	ret = cmh_tm_submit_sync_tmo(vcq, HCQ_VCQ_CMDS_MIN, 1, d.mbx_idx,
> +				     cmh_tm_slow_op_timeout_jiffies());
> +
> +out_unmap:
> +	if (!cmh_dma_map_error(pk_dma))
> +		cmh_dma_unmap_single(pk_dma, pk_sz, DMA_TO_DEVICE);
> +	if (!cmh_dma_map_error(m_dma))
> +		cmh_dma_unmap_single(m_dma, dlen, DMA_TO_DEVICE);
> +	if (!cmh_dma_map_error(sig_dma))
> +		cmh_dma_unmap_single(sig_dma, sig_sz, DMA_TO_DEVICE);
> +
> +out_free:
> +	kfree(pk_buf);
> +	kfree(m_buf);
> +	kfree(sig_buf);
> +	return ret;
> +}

[Severity: High]
Can a hardware timeout cause a use-after-free? Freeing m_buf, pk_buf, and
sig_buf immediately after a timeout might allow a delayed hardware DMA
completion to access freed memory.

> diff --git a/drivers/crypto/cmh/cmh_pqc_xmss.c b/drivers/crypto/cmh/cmh_pqc_xmss.c
> new file mode 100644
> index 0000000000000..50de1ef0f488c
> --- /dev/null
> +++ b/drivers/crypto/cmh/cmh_pqc_xmss.c
> @@ -0,0 +1,238 @@
> [ ... ]
> +static int cmh_xmss_verify(struct crypto_sig *tfm,
> +			   const void *src, unsigned int slen,
> +			   const void *digest, unsigned int dlen)
> +{
> [ ... ]
> +	if (!dlen || dlen > XMSS_MAX_MSG_LEN)
> +		return -EINVAL;

[Severity: Medium]
Will this return -EINVAL for perfectly valid 0-length messages?

> +
> +	sig_buf = kmemdup(src, slen, GFP_KERNEL);
> [ ... ]
> +	/* XMSS verify traverses Merkle hash chains -- inherently slow */
> +	ret = cmh_tm_submit_sync_tmo(vcq, XMSS_VCQ_CMDS, 1, d.mbx_idx,
> +				     cmh_tm_slow_op_timeout_jiffies());
> +
> +out_unmap:
> +	if (!cmh_dma_map_error(pk_dma))
> +		cmh_dma_unmap_single(pk_dma, ctx->pub_key_len, DMA_TO_DEVICE);
> +	if (!cmh_dma_map_error(m_dma))
> +		cmh_dma_unmap_single(m_dma, dlen, DMA_TO_DEVICE);
> +	if (!cmh_dma_map_error(sig_dma))
> +		cmh_dma_unmap_single(sig_dma, slen, DMA_TO_DEVICE);
> +
> +out_free:
> +	kfree(pk_buf);
> +	kfree(m_buf);
> +	kfree(sig_buf);
> +	return ret;
> +}

[Severity: High]
Does this error path introduce a use-after-free risk? If the hardware stalls
and cmh_tm_submit_sync_tmo() returns -ETIMEDOUT, these buffers are freed. A
subsequent hardware recovery would access memory that is no longer allocated.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260806195519.2703224-1-skrishnamoorthy@rambus.com?part=16

  reply	other threads:[~2026-08-06 20:43 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-06 19:54 [PATCH v3 00/19] crypto: cmh - add Rambus CryptoManager Hub driver Saravanakrishnan Krishnamoorthy
2026-08-06 19:55 ` [PATCH v3 01/19] dt-bindings: crypto: add Rambus CryptoManager Hub Saravanakrishnan Krishnamoorthy
2026-08-06 20:01   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 02/19] crypto: cmh - add core platform driver Saravanakrishnan Krishnamoorthy
2026-08-06 20:11   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 03/19] crypto: cmh - add key provisioning and management Saravanakrishnan Krishnamoorthy
2026-08-06 20:17   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 04/19] crypto: cmh - add SHA-2/SHA-3/SHAKE ahash Saravanakrishnan Krishnamoorthy
2026-08-06 20:12   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 05/19] crypto: cmh - add HMAC ahash Saravanakrishnan Krishnamoorthy
2026-08-06 20:09   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 06/19] crypto: cmh - add CSHAKE/KMAC ahash Saravanakrishnan Krishnamoorthy
2026-08-06 20:10   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 07/19] crypto: cmh - add SM3 ahash Saravanakrishnan Krishnamoorthy
2026-08-06 20:07   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 08/19] crypto: cmh - add AES skcipher/aead/cmac Saravanakrishnan Krishnamoorthy
2026-08-06 20:10   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 09/19] crypto: cmh - add SM4 skcipher/aead/cmac/xcbc Saravanakrishnan Krishnamoorthy
2026-08-06 20:09   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 10/19] crypto: cmh - add ChaCha20-Poly1305 Saravanakrishnan Krishnamoorthy
2026-08-06 20:12   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 11/19] crypto: cmh - add DRBG hwrng Saravanakrishnan Krishnamoorthy
2026-08-06 20:17   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 12/19] crypto: cmh - add RSA akcipher Saravanakrishnan Krishnamoorthy
2026-08-06 20:18   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 13/19] crypto: cmh - add ECDSA/SM2 sig Saravanakrishnan Krishnamoorthy
2026-08-06 20:24   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 14/19] crypto: cmh - add ECDH/X25519 kpp Saravanakrishnan Krishnamoorthy
2026-08-06 20:34   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 15/19] crypto: cmh - add ML-KEM/ML-DSA (QSE) Saravanakrishnan Krishnamoorthy
2026-08-06 20:24   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 16/19] crypto: cmh - add SLH-DSA/LMS/XMSS (HCQ) Saravanakrishnan Krishnamoorthy
2026-08-06 20:43   ` sashiko-bot [this message]
2026-08-06 19:55 ` [PATCH v3 17/19] Documentation: ioctl: add CMH ioctl documentation and register 'J' Saravanakrishnan Krishnamoorthy
2026-08-06 20:25   ` sashiko-bot
2026-08-06 19:55 ` [PATCH v3 18/19] selftests: crypto: cmh - add kselftest for management ioctl Saravanakrishnan Krishnamoorthy
2026-08-06 19:55 ` [PATCH v3 19/19] MAINTAINERS: add Rambus CryptoManager Hub (CMH) Saravanakrishnan Krishnamoorthy

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