Re: [PATCH v2 04/12] clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Type correctness regression: left shift of a signed integer without casting
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--- Patch [4]: [PATCH v2 04/12] clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags ---
commit 8da3393b838b4e4b6fe1ccda790022d6a599db23
Author: Luo Jie <jie.luo@oss.qualcomm.com>

clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags

This commit adds a flags field to struct clk_regmap_div and passes it to
clock divider functions to support CLK_DIVIDER_* behavior variants. It also
updates div_set_rate() to handle negative error codes from divider_get_val()
by changing the div variable from an unsigned to a signed integer.

> diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-regmap-divider.c
> index 672e82caf2050..fe4542b5bd580 100644
> --- a/drivers/clk/qcom/clk-regmap-divider.c
> +++ b/drivers/clk/qcom/clk-regmap-divider.c

[ ... ]

> @@ -43,10 +44,12 @@ static int div_set_rate(struct clk_hw *hw, unsigned long rate,
>  {
>  	struct clk_regmap_div *divider = to_clk_regmap_div(hw);
>  	struct clk_regmap *clkr = &divider->clkr;
> -	u32 div;
> +	int div;
>  
>  	div = divider_get_val(rate, parent_rate, NULL, divider->width,
> -			      CLK_DIVIDER_ROUND_CLOSEST);
> +			      CLK_DIVIDER_ROUND_CLOSEST | divider->flags);
> +	if (div < 0)
> +		return div;
>  
>  	return regmap_update_bits(clkr->regmap, divider->reg,
>  				  (BIT(divider->width) - 1) << divider->shift,
>  				  div << divider->shift);

[Severity: Low]
Since div was changed to a signed int to handle error codes, should it be cast
to an unsigned type before being shifted here? 

Left-shifting a signed integer without casting can trigger static analysis
warnings, or technically undefined behavior in standard C if the value
overflows into the sign bit.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com?part=4