From: Vladislav Leonov <vlad@zlab.su>
To: linux-rockchip@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org,
Simon Glass <sjg@chromium.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Vladislav Leonov <vlad@zlab.su>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Rob Herring <robh@kernel.org>
Subject: [PATCH 25/25] ARM: dts: rockchip: Add PWM nodes for RV1106
Date: Mon, 10 Aug 2026 15:11:16 +0300 [thread overview]
Message-ID: <20260810121121.210040-26-vlad@zlab.su> (raw)
In-Reply-To: <20260810121121.210040-1-vlad@zlab.su>
Add the 12 PWM controller nodes (pwm0-pwm11) for RV1106, along with
their aliases.
Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---
arch/arm/boot/dts/rockchip/rv1106.dtsi | 159 +++++++++++++++++++++++++
1 file changed, 159 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index 12e87d25c72b..d7959158f8a0 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -30,6 +30,18 @@ aliases {
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
+ pwm0 = &pwm0;
+ pwm1 = &pwm1;
+ pwm2 = &pwm2;
+ pwm3 = &pwm3;
+ pwm4 = &pwm4;
+ pwm5 = &pwm5;
+ pwm6 = &pwm6;
+ pwm7 = &pwm7;
+ pwm8 = &pwm8;
+ pwm9 = &pwm9;
+ pwm10 = &pwm10;
+ pwm11 = &pwm11;
spi0 = &spi0;
spi1 = &spi1;
};
@@ -189,6 +201,104 @@ i2c1: i2c@ff320000 {
status = "disabled";
};
+ pwm0: pwm@ff350000 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff350000 0x10>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0m0_pins>;
+ clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@ff350010 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff350010 0x10>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1m0_pins>;
+ clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm2: pwm@ff350020 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff350020 0x10>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_pins>;
+ clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm3: pwm@ff350030 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff350030 0x10>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3m0_pins>;
+ clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm4: pwm@ff360000 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff360000 0x10>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm4m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm5: pwm@ff360010 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff360010 0x10>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm5m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm6: pwm@ff360020 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff360020 0x10>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm6m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm7: pwm@ff360030 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff360030 0x10>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm7m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
gpio0_ioc: syscon@ff388000 {
compatible = "rockchip,rv1106-gpio0-ioc", "syscon";
reg = <0xff388000 0x8000>;
@@ -304,6 +414,55 @@ i2c4: i2c@ff470000 {
status = "disabled";
};
+ pwm8: pwm@ff490000 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff490000 0x10>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm8m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm9: pwm@ff490010 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff490010 0x10>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm9m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm10: pwm@ff490020 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff490020 0x10>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm10m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm11: pwm@ff490030 {
+ compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff490030 0x10>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm11m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
uart0: serial@ff4a0000 {
compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
reg = <0xff4a0000 0x100>;
--
2.47.3
next prev parent reply other threads:[~2026-08-10 12:16 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-10 12:10 [PATCH 00/25] ARM: rockchip: Add peripheral support for RV1106 Vladislav Leonov
2026-08-10 12:10 ` [PATCH 01/25] dt-bindings: reset: Add RV1106 CRU reset definitions Vladislav Leonov
2026-08-10 12:10 ` [PATCH 02/25] clk: rockchip: Add reset controller support for RV1106 Vladislav Leonov
2026-08-10 12:10 ` [PATCH 03/25] ARM: dts: rockchip: Add reset bindings to RV1106 Vladislav Leonov
2026-08-10 12:10 ` [PATCH 04/25] dt-bindings: net: rockchip-dwmac: add RV1106 compatible Vladislav Leonov
2026-08-10 12:10 ` [PATCH 05/25] net: ethernet: stmicro: stmmac: dwmac-rk: Add RV1106 support Vladislav Leonov
2026-08-10 12:10 ` [PATCH 06/25] ARM: dts: rockchip: Add Ethernet GMAC node for RV1106 Vladislav Leonov
2026-08-10 12:10 ` [PATCH 07/25] dt-bindings: phy: rockchip,inno-usb2phy: Add RV1106 compatible Vladislav Leonov
2026-08-10 12:10 ` [PATCH 08/25] phy: rockchip: inno-usb2: Add support for RV1106 Vladislav Leonov
2026-08-10 12:11 ` [PATCH 09/25] dt-bindings: usb: rockchip,dwc3: add RV1106 SoC support Vladislav Leonov
2026-08-10 12:11 ` [PATCH 10/25] ARM: dts: rockchip: Add USB2 PHY and USB3-OTG (DWC3) nodes for RV1106 Vladislav Leonov
2026-08-10 12:11 ` [PATCH 11/25] dt-bindings: i2c: rk3x: Add RV1106 compatible Vladislav Leonov
2026-08-10 12:11 ` [PATCH 12/25] ARM: dts: rockchip: Add I2C nodes for RV1106 Vladislav Leonov
2026-08-10 12:11 ` [PATCH 13/25] ARM: dts: rockchip: Add DMAC node " Vladislav Leonov
2026-08-10 12:11 ` [PATCH 14/25] ARM: dts: rockchip: Add DMA support to UART nodes Vladislav Leonov
2026-08-10 12:11 ` [PATCH 15/25] dt-bindings: clock: rockchip: Add SCLK_IN_SPI1 for RV1106 Vladislav Leonov
2026-08-10 12:11 ` [PATCH 16/25] clk: rockchip: Add SCLK_IN_SPI1 gate " Vladislav Leonov
2026-08-10 12:11 ` [PATCH 17/25] dt-bindings: spi: rockchip: Add RV1106 compatible Vladislav Leonov
2026-08-10 12:25 ` Mark Brown
2026-08-10 12:11 ` [PATCH 18/25] spi: rockchip: Add support for RV1106 Vladislav Leonov
2026-08-10 12:11 ` [PATCH 19/25] ARM: dts: rockchip: Add SPI nodes " Vladislav Leonov
2026-08-10 12:11 ` [PATCH 20/25] dt-bindings: rng: rockchip: Add RV1106 compatible Vladislav Leonov
2026-08-10 12:11 ` [PATCH 21/25] ARM: dts: rockchip: Add RNG node for RV1106 Vladislav Leonov
2026-08-10 12:11 ` [PATCH 22/25] ARM: dts: rockchip: Add SDMMC1 " Vladislav Leonov
2026-08-10 12:11 ` [PATCH 23/25] ARM: dts: rockchip: add arm,cpu-registers-not-fw-configured to RV1106 timer node Vladislav Leonov
2026-08-10 12:11 ` [PATCH 24/25] dt-bindings: pwm: rockchip: Add RV1106 compatible Vladislav Leonov
2026-08-10 12:11 ` Vladislav Leonov [this message]
2026-08-10 18:35 ` [PATCH 00/25] ARM: rockchip: Add peripheral support for RV1106 Jakub Kicinski
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