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From: Santhosh Kumar K <s-k6@ti.com>
To: <broonie@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
	<conor+dt@kernel.org>, <miquel.raynal@bootlin.com>,
	<richard@nod.at>, <vigneshr@ti.com>, <pratyush@kernel.org>,
	<mwalle@kernel.org>, <takahiro.kuwano@infineon.com>
Cc: <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
	<praneeth@ti.com>, <u-kumar1@ti.com>, <a-dutta@ti.com>,
	<s-k6@ti.com>
Subject: [PATCH v7 14/18] spi: cadence-quadspi: reprogram PHY DLL on runtime resume
Date: Wed, 12 Aug 2026 00:03:09 +0530	[thread overview]
Message-ID: <20260811183313.1550425-15-s-k6@ti.com> (raw)
In-Reply-To: <20260811183313.1550425-1-s-k6@ti.com>

The PHY DLL loses its programmed delay values and lock when the OSPI
controller is power-gated during runtime suspend. On resume,
cqspi_controller_init() reinitialises the controller but does not
touch the PHY DLL registers, leaving the DLL in an unlocked state.
Any subsequent PHY read or write would then fail at the cqspi_resync_dll()
call inside cqspi_tune_phy().

After the controller re-initialisation, iterate over all chip selects
and reprogram the DLL with each CS's stored calibrated RX/TX tap counts,
then resync to relock it. One invocation per calibrated CS allows each
calibration to be independently validated after resume. DLL resync
failure is non-fatal: a warning is emitted and resume continues, so the
system degrades to non-PHY speed rather than blocking the resume path.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
---
 drivers/spi/spi-cadence-quadspi.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index d4181b501d8d..c78d4ce1c930 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -4017,7 +4017,7 @@ static int cqspi_runtime_suspend(struct device *dev)
 static int cqspi_runtime_resume(struct device *dev)
 {
 	struct cqspi_st *cqspi = dev_get_drvdata(dev);
-	int ret;
+	int cs, ret;
 
 	ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks);
 	if (ret)
@@ -4030,6 +4030,23 @@ static int cqspi_runtime_resume(struct device *dev)
 
 	cqspi->current_cs = -1;
 	cqspi->sclk = 0;
+
+	for (cs = 0; cs < CQSPI_MAX_CHIPSELECT; cs++) {
+		struct cqspi_flash_pdata *f_pdata = &cqspi->f_pdata[cs];
+
+		if (!f_pdata->use_tuned_phy)
+			continue;
+
+		cqspi_phy_set_dll_master(cqspi);
+
+		cqspi_set_dll(cqspi->iobase, f_pdata->phy_setting.rx,
+			      f_pdata->phy_setting.tx);
+		ret = cqspi_resync_dll(cqspi);
+		if (ret)
+			dev_warn(dev, "cs%d: PHY DLL resync failed on resume: %d\n",
+				 cs, ret);
+	}
+
 	return 0;
 }
 
-- 
2.34.1


  parent reply	other threads:[~2026-08-11 18:35 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-11 18:32 [PATCH v7 00/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-11 18:32 ` [PATCH v7 01/18] spi: dt-bindings: add spi-max-post-config-frequency-hz property Santhosh Kumar K
2026-08-11 18:32 ` [PATCH v7 02/18] spi: dt-bindings: add spi-phy-pattern-partition property Santhosh Kumar K
2026-08-11 18:32 ` [PATCH v7 03/18] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz Santhosh Kumar K
2026-08-11 18:32 ` [PATCH v7 04/18] spi: spi-mem: teach spi_mem_adjust_op_freq() about post-config ops Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 05/18] spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning() Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 06/18] spi: cadence-quadspi: move cqspi_readdata_capture earlier Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 07/18] spi: cadence-quadspi: add DQS support to read data capture Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 08/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 09/18] spi: cadence-quadspi: skip DDR PHY tuning for 2-byte-address ops (i2383) Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 10/18] spi: cadence-quadspi: refactor direct read path for PHY support Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 11/18] spi: cadence-quadspi: enable PHY for direct reads Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 12/18] spi: cadence-quadspi: enable PHY for indirect writes Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 13/18] spi: cadence-quadspi: reprogram CS timing on every chip-select switch Santhosh Kumar K
2026-08-11 18:33 ` Santhosh Kumar K [this message]
2026-08-11 18:33 ` [PATCH v7 15/18] mtd: spinand: extract variant ranking logic into spinand_op_find_best_variant() Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 16/18] mtd: spinand: negotiate optimal controller operating point before dirmap creation Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 17/18] mtd: spi-nor: extract read op template construction into helper Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 18/18] mtd: spi-nor: run controller optimization before dirmap creation Santhosh Kumar K

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