[PATCH 0/6] Add SpacemiT K1 USB2.0 controllers support

[PATCH 0/6] Add SpacemiT K1 USB2.0 controllers support

[Junzhong Pan]

The SpacemiT K1 SoC has two USB2.0 controllers, one has Dual-Role
support, but the hardware has no internal OTG registers, the other is
Host only. These controllers are compatible with Chipidea USB2 driver
with some flags set and reset control support.

This series is based on 7.2-rc1 and has been tested on Banana Pi F3
development board.

A self-powered USB device/hub is needed to test the host function of the
dual-role controller on Banana Pi F3, a MINI-PCIe USB2.0 module (a
cellular module e.g.) is needed to test the host only controller.

Signed-off-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
---
Junzhong Pan (6):
      dt-bindings: usb: ci-hdrc-usb2: add spacemit,k1-usb2 compatible
      usb: chipidea: usb2: add optional reset support
      usb: chipidea: usb2: add SpacemiT K1 support
      riscv: dts: spacemit: add USB2.0 controller nodes for K1
      riscv: dts: spacemit: enable USB2.0 controllers on BananaPi F3
      riscv: defconfig: enable ChipIdea USB controller support

 .../devicetree/bindings/usb/ci-hdrc-usb2.yaml      |  1 +
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts    | 16 +++++++++
 arch/riscv/boot/dts/spacemit/k1.dtsi               | 40 ++++++++++++++++++++++
 arch/riscv/configs/defconfig                       |  4 +++
 drivers/usb/chipidea/ci_hdrc_usb2.c                | 16 +++++++++
 5 files changed, 77 insertions(+)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260812-b4-spacemit-k1-usb2-97adfc283d58

Best regards,
-- 
Junzhong Pan <panjunzhong@linux.spacemit.com>

[PATCH 1/6] dt-bindings: usb: ci-hdrc-usb2: add spacemit,k1-usb2 compatible

[Junzhong Pan]

The USB2.0 controller on the SpacemiT K1 SoC is dual-role capable but
has no internal OTG registers, this requires flags which disable
related features set in platform data. Add a compatible string to match
the platform data.

Signed-off-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
---
 Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml
index 620b564914d4..6f8d88a0681d 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml
@@ -25,6 +25,7 @@ properties:
           - nvidia,tegra124-udc
           - nxp,s32g2-usb
           - qcom,ci-hdrc
+          - spacemit,k1-usb2
       - items:
           - enum:
               - nvidia,tegra114-ehci

-- 
2.34.1

Re: [PATCH 1/6] dt-bindings: usb: ci-hdrc-usb2: add spacemit,k1-usb2 compatible

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 75 bytes --]

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH 2/6] usb: chipidea: usb2: add optional reset support

[Junzhong Pan]

The USB2 controller of SpacemiT K1 SoC requires reset support, to keep
compatibility, add optional reset support.

Signed-off-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
---
 drivers/usb/chipidea/ci_hdrc_usb2.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/usb/chipidea/ci_hdrc_usb2.c b/drivers/usb/chipidea/ci_hdrc_usb2.c
index 8ffa1e95d8e8..00d575cd2955 100644
--- a/drivers/usb/chipidea/ci_hdrc_usb2.c
+++ b/drivers/usb/chipidea/ci_hdrc_usb2.c
@@ -12,6 +12,7 @@
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/property.h>
+#include <linux/reset.h>
 #include <linux/usb/chipidea.h>
 #include <linux/usb/hcd.h>
 #include <linux/usb/ulpi.h>
@@ -21,6 +22,7 @@
 struct ci_hdrc_usb2_priv {
 	struct platform_device	*ci_pdev;
 	struct clk		*clk;
+	struct reset_control	*reset;
 };
 
 static const struct ci_hdrc_platform_data ci_default_pdata = {
@@ -80,6 +82,12 @@ static int ci_hdrc_usb2_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	priv->reset = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
+	if (IS_ERR(priv->reset)) {
+		ret = PTR_ERR(priv->reset);
+		goto clk_err;
+	}
+
 	ci_pdata->name = dev_name(dev);
 
 	priv->ci_pdev = ci_hdrc_add_device(dev, pdev->resource,

-- 
2.34.1

Re: [PATCH 2/6] usb: chipidea: usb2: add optional reset support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Teardown order inversion between manual clock disable and devm-managed reset assertion.
--

--- Patch [2]: [PATCH 2/6] usb: chipidea: usb2: add optional reset support ---
commit 5129acb0e56d5e6166124800f0bd1996cf88389b
Author: Junzhong Pan <panjunzhong@linux.spacemit.com>

usb: chipidea: usb2: add optional reset support

This commit adds optional reset control support for the USB2 controller
found on the SpacemiT K1 SoC.

> diff --git a/drivers/usb/chipidea/ci_hdrc_usb2.c b/drivers/usb/chipidea/ci_hdrc_usb2.c
> index 8ffa1e95d8e86..00d575cd29557 100644
> --- a/drivers/usb/chipidea/ci_hdrc_usb2.c
> +++ b/drivers/usb/chipidea/ci_hdrc_usb2.c
[ ... ]
> @@ -80,6 +82,12 @@ static int ci_hdrc_usb2_probe(struct platform_device *pdev)
>  		return ret;
>  	}
>  
> +	priv->reset = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
> +	if (IS_ERR(priv->reset)) {
> +		ret = PTR_ERR(priv->reset);
> +		goto clk_err;
> +	}
> +

[Severity: High]
Does this create a teardown order inversion later in ci_hdrc_usb2_probe()
or ci_hdrc_usb2_remove()?

Because the reset is acquired using
devm_reset_control_get_optional_exclusive_deasserted(), the devres cleanup
will automatically assert the reset after probe failure or device removal.

However, looking at the rest of ci_hdrc_usb2_probe(), if ci_hdrc_add_device()
fails, the code jumps to clk_err and manually calls clk_disable_unprepare()
before the devres cleanup runs:

ci_hdrc_usb2_probe() {
	...
	priv->ci_pdev = ci_hdrc_add_device(...);
	if (IS_ERR(priv->ci_pdev)) {
		...
		goto clk_err;
	}
	...
clk_err:
	clk_disable_unprepare(priv->clk);
	return ret;
}

This means the reset will be asserted after the clock is disabled. On many
architectures, asserting a peripheral reset while its clock is disabled can
cause bus lockups or system hangs.

This same inversion appears to affect device unbind as well, since
ci_hdrc_usb2_remove() manually disables the clock before devres runs.

Would using devres for the clock enablement ensure standard LIFO teardown
ordering?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260812-b4-spacemit-k1-usb2-v1-0-f28cf29e522b@linux.spacemit.com?part=2

Re: [PATCH 2/6] usb: chipidea: usb2: add optional reset support

[Junzhong Pan]

> ci_hdrc_usb2_probe() {
> 	...
> 	priv->ci_pdev = ci_hdrc_add_device(...);
> 	if (IS_ERR(priv->ci_pdev)) {
> 		...
> 		goto clk_err;
> 	}
> 	...
> clk_err:
> 	clk_disable_unprepare(priv->clk);
> 	return ret;
> }
> 
> This means the reset will be asserted after the clock is disabled. On many
> architectures, asserting a peripheral reset while its clock is disabled can
> cause bus lockups or system hangs.
> 
> This same inversion appears to affect device unbind as well, since
> ci_hdrc_usb2_remove() manually disables the clock before devres runs.
> 
> Would using devres for the clock enablement ensure standard LIFO teardown
> ordering?

Okay, I will add a preparatory patch to the series in v2 to use devres for
clock before the reset patch. thank you sashiko.

[PATCH 3/6] usb: chipidea: usb2: add SpacemiT K1 support

[Junzhong Pan]

Add a compatible for SpacemiT K1, and add platform data with correct
flag since the hardware doesn't have internal otg register support.

Signed-off-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
---
 drivers/usb/chipidea/ci_hdrc_usb2.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/usb/chipidea/ci_hdrc_usb2.c b/drivers/usb/chipidea/ci_hdrc_usb2.c
index 00d575cd2955..70c5ce750519 100644
--- a/drivers/usb/chipidea/ci_hdrc_usb2.c
+++ b/drivers/usb/chipidea/ci_hdrc_usb2.c
@@ -40,10 +40,18 @@ static const struct ci_hdrc_platform_data ci_zevio_pdata = {
 	.flags		= CI_HDRC_REGS_SHARED | CI_HDRC_FORCE_FULLSPEED,
 };
 
+static const struct ci_hdrc_platform_data ci_k1_pdata = {
+	.capoffset	= DEF_CAPOFFSET,
+	.flags		= CI_HDRC_DISABLE_STREAMING |
+			  CI_HDRC_FORCE_VBUS_ACTIVE_ALWAYS |
+			  CI_HDRC_DUAL_ROLE_NOT_OTG,
+};
+
 static const struct of_device_id ci_hdrc_usb2_of_match[] = {
 	{ .compatible = "chipidea,usb2" },
 	{ .compatible = "xlnx,zynq-usb-2.20a", .data = &ci_zynq_pdata },
 	{ .compatible = "lsi,zevio-usb", .data = &ci_zevio_pdata },
+	{ .compatible = "spacemit,k1-usb2", .data = &ci_k1_pdata },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, ci_hdrc_usb2_of_match);

-- 
2.34.1

[PATCH 4/6] riscv: dts: spacemit: add USB2.0 controller nodes for K1

[Junzhong Pan]

The SpacemiT K1 SoC has two ChipIdea USB2.0 controllers.
- USB2.0 Dual-Role
- usb2.0 Host Only

Add the controller and PHY nodes.

Signed-off-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
---
 arch/riscv/boot/dts/spacemit/k1.dtsi | 40 ++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 08a0f28d011f..aa35a3489250 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -449,6 +449,22 @@ syscon_rcpu2: system-controller@c0888000 {
 			#reset-cells = <1>;
 		};
 
+		usbphy0: phy@c0940000 {
+			compatible = "spacemit,k1-usb2-phy";
+			reg = <0x0 0xc0940000 0x0 0x200>;
+			clocks = <&syscon_apmu CLK_USB_AXI>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usbphy1: phy@c09c0000 {
+			compatible = "spacemit,k1-usb2-phy";
+			reg = <0x0 0xc09c0000 0x0 0x200>;
+			clocks = <&syscon_apmu CLK_USB_P1>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		usbphy2: phy@c0a30000 {
 			compatible = "spacemit,k1-usb2-phy";
 			reg = <0x0 0xc0a30000 0x0 0x200>;
@@ -1291,6 +1307,30 @@ storage-bus {
 			#size-cells = <2>;
 			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
 
+			usb2_0: usb@c0900000 {
+				compatible = "spacemit,k1-usb2";
+				reg = <0x0 0xc0900000 0x0 0x4100>;
+				interrupts = <105>;
+				clocks = <&syscon_apmu CLK_USB_AXI>;
+				resets = <&syscon_apmu RESET_USB_AXI>;
+				phys = <&usbphy0>;
+				phy-names = "usb-phy";
+				dr_mode = "otg";
+				status = "disabled";
+			};
+
+			usb2_1: usb@c0980000 {
+				compatible = "spacemit,k1-usb2";
+				reg = <0x0 0xc0980000 0x0 0x4100>;
+				interrupts = <118>;
+				clocks = <&syscon_apmu CLK_USB_P1>;
+				resets = <&syscon_apmu RESET_USBP1_AXI>;
+				phys = <&usbphy1>;
+				phy-names = "usb-phy";
+				dr_mode = "host";
+				status = "disabled";
+			};
+
 			usb_dwc3: usb@c0a00000 {
 				compatible = "spacemit,k1-dwc3";
 				reg = <0x0 0xc0a00000 0x0 0x10000>;

-- 
2.34.1

Re: [PATCH 4/6] riscv: dts: spacemit: add USB2.0 controller nodes for K1

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The newly added `usb2_0` and `usb2_1` controllers are instantiated under the `storage-bus` node, which has a restrictive `dma-ranges` property that excludes system RAM, preventing DMA operations for these controllers.
--

--- Patch [4]: [PATCH 4/6] riscv: dts: spacemit: add USB2.0 controller nodes for K1 ---
commit 574278a69410138bf5c5e246489a12433bf57db8
Author: Junzhong Pan <panjunzhong@linux.spacemit.com>

riscv: dts: spacemit: add USB2.0 controller nodes for K1

This commit adds two ChipIdea USB2.0 controllers to the SpacemiT K1
SoC device tree. One controller is configured for Dual-Role (OTG)
and the other is Host Only.

> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index 08a0f28d011fe..aa35a34892503 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi

[ ... ]

> @@ -1291,6 +1307,30 @@ storage-bus {
>  			#size-cells = <2>;
>  			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
>  
> +			usb2_0: usb@c0900000 {
> +				compatible = "spacemit,k1-usb2";
> +				reg = <0x0 0xc0900000 0x0 0x4100>;
> +				interrupts = <105>;
> +				clocks = <&syscon_apmu CLK_USB_AXI>;
> +				resets = <&syscon_apmu RESET_USB_AXI>;
> +				phys = <&usbphy0>;
> +				phy-names = "usb-phy";
> +				dr_mode = "otg";
> +				status = "disabled";
> +			};
> +
> +			usb2_1: usb@c0980000 {

[Severity: High]
This isn't a bug introduced by this patch, but will these new USB controllers
fail to perform DMA operations because of the storage-bus node's dma-ranges
property?

The parent storage-bus node defines:
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;

This restricts DMA accesses to physical addresses between 0x0 and 0x7FFFFFFF.
Since the system RAM on this SoC starts at 0x100000000 (above the 4GB
boundary), will the kernel's DMA subsystem reject mappings for data buffers
or descriptors located in RAM?

Placing these new DMA-capable USB nodes under storage-bus seems to guarantee
they will fail to map memory.

> +				compatible = "spacemit,k1-usb2";
> +				reg = <0x0 0xc0980000 0x0 0x4100>;
> +				interrupts = <118>;
> +				clocks = <&syscon_apmu CLK_USB_P1>;
> +				resets = <&syscon_apmu RESET_USBP1_AXI>;
> +				phys = <&usbphy1>;
> +				phy-names = "usb-phy";
> +				dr_mode = "host";
> +				status = "disabled";
> +			};
> +
>  			usb_dwc3: usb@c0a00000 {
>  				compatible = "spacemit,k1-dwc3";
>  				reg = <0x0 0xc0a00000 0x0 0x10000>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260812-b4-spacemit-k1-usb2-v1-0-f28cf29e522b@linux.spacemit.com?part=4

Re: [PATCH 4/6] riscv: dts: spacemit: add USB2.0 controller nodes for K1

[Junzhong Pan]

On 8/12/2026 5:51 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> [...]
>> @@ -1291,6 +1307,30 @@ storage-bus {
>>  			#size-cells = <2>;
>>  			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
>>  
>> +			usb2_0: usb@c0900000 {
>> +				compatible = "spacemit,k1-usb2";
>> +				reg = <0x0 0xc0900000 0x0 0x4100>;
>> +				interrupts = <105>;
>> +				clocks = <&syscon_apmu CLK_USB_AXI>;
>> +				resets = <&syscon_apmu RESET_USB_AXI>;
>> +				phys = <&usbphy0>;
>> +				phy-names = "usb-phy";
>> +				dr_mode = "otg";
>> +				status = "disabled";
>> +			};
>> +
>> +			usb2_1: usb@c0980000 {
> 
> [Severity: High]
> This isn't a bug introduced by this patch, but will these new USB controllers
> fail to perform DMA operations because of the storage-bus node's dma-ranges
> property?
> 
> The parent storage-bus node defines:
> dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
> 
> This restricts DMA accesses to physical addresses between 0x0 and 0x7FFFFFFF.
> Since the system RAM on this SoC starts at 0x100000000 (above the 4GB
> boundary), will the kernel's DMA subsystem reject mappings for data buffers
> or descriptors located in RAM?
> 
> Placing these new DMA-capable USB nodes under storage-bus seems to guarantee
> they will fail to map memory.
> 
>> +				compatible = "spacemit,k1-usb2";
>> +				reg = <0x0 0xc0980000 0x0 0x4100>;
>> +				interrupts = <118>;
>> +				clocks = <&syscon_apmu CLK_USB_P1>;
>> +				resets = <&syscon_apmu RESET_USBP1_AXI>;
>> +				phys = <&usbphy1>;
>> +				phy-names = "usb-phy";
>> +				dr_mode = "host";
>> +				status = "disabled";
>> +			};
>> +
>>  			usb_dwc3: usb@c0a00000 {
>>  				compatible = "spacemit,k1-dwc3";
>>  				reg = <0x0 0xc0a00000 0x0 0x10000>;
> 

I am pretty sure this would not be a problem. The SpacemiT K1 have 0~2G as part
of the system RAM, the default dma mask of these device would be 32bit, and there
is swiotlb would help with the mapping of high memory. So the DMA configuration
correctly works here. Thank you sashiko.

[PATCH 5/6] riscv: dts: spacemit: enable USB2.0 controllers on BananaPi F3

[Junzhong Pan]

On BananaPi F3, usb2_0 is connected to a Type-C connector at device
mode by default. This port have no VBUS supply capability, thus host
mode only works with self-powered device or hub. User could switch the
role in sysfs.

And the usb2_1 is connected to the USB2.0 pins of the Mini PCIe slot to
support cellular modules.

Signed-off-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
---
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 72f77e9edd63..fd0f96262009 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -350,6 +350,22 @@ &uart0 {
 	status = "okay";
 };
 
+&usbphy0 {
+	status = "okay";
+};
+
+&usb2_0 {
+	status = "okay";
+};
+
+&usbphy1 {
+	status = "okay";
+};
+
+&usb2_1 {
+	status = "okay";
+};
+
 &usbphy2 {
 	status = "okay";
 };

-- 
2.34.1

[PATCH 6/6] riscv: defconfig: enable ChipIdea USB controller support

[Junzhong Pan]

Enable the ChipIdea USB2 controller and SpacemiT K1 USB2 PHY to support
USB2.0 controllers on the SpacemiT K1 SoC.

Signed-off-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
---
 arch/riscv/configs/defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 74ba5acc12a4..6e8c9f620408 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -219,6 +219,9 @@ CONFIG_USB_CDNS3_HOST=y
 CONFIG_USB_CDNS3_STARFIVE=m
 CONFIG_USB_MUSB_HDRC=m
 CONFIG_USB_MUSB_SUNXI=m
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
 CONFIG_NOP_USB_XCEIV=m
 CONFIG_USB_GADGET=y
 CONFIG_USB_CONFIGFS=m
@@ -269,6 +272,7 @@ CONFIG_PWM=y
 CONFIG_PWM_PXA=m
 CONFIG_THEAD_C900_ACLINT_SSWI=y
 CONFIG_PHY_SUN4I_USB=m
+CONFIG_PHY_SPACEMIT_K1_USB2=y
 CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m
 CONFIG_PHY_STARFIVE_JH7110_PCIE=m
 CONFIG_PHY_STARFIVE_JH7110_USB=m

-- 
2.34.1