From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org,
dfustini@oss.tenstorrent.com, michal.simek@amd.com,
junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com,
akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn,
luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn,
nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com,
greentime.hu@sifive.com, robin.randhawa@sifive.com,
scott@riscstar.com, dave.patel@riscstar.com,
raymond.mao@riscstar.com, anup@brainfault.org,
pawandeep.oza@oss.qualcomm.com,
Yu-Chien Peter Lin <peter.lin@sifive.com>
Subject: [RFC PATCH v3 1/3] dt-bindings: riscv: Add Worlds ISA extensions
Date: Wed, 12 Aug 2026 20:21:29 +0800 [thread overview]
Message-ID: <20260812122131.1534906-2-peter.lin@sifive.com> (raw)
In-Reply-To: <20260812122131.1534906-1-peter.lin@sifive.com>
Add DT bindings for RISC-V Worlds ISA extensions
(Smwid, Smlwidlist, Smlwid, Smwiddeleg, Sswid) and
enforce their architectural dependency rules in the
schema.
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
Changes v2->v3:
- Add extension dependency rules
- Fix alphabetical order
---
.../devicetree/bindings/riscv/extensions.yaml | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 5ffc40d599c0..0408d1116527 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -181,6 +181,18 @@ properties:
changes to interrupts as frozen at commit ccbddab ("Merge pull
request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
+ - const: smlwid
+ description: |
+ The standard Smlwid extension for M-mode control of lower
+ privilege World ID via the mlwid CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
+ - const: smlwidlist
+ description: |
+ The standard Smlwidlist extension for M-mode control of lower
+ privilege World IDs via the mlwidlist CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
- const: smmpm
description: |
The standard Smmpm extension for M-mode pointer masking as
@@ -199,6 +211,17 @@ properties:
added by other RISC-V extensions in H/S/VS/U/VU modes and as
ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
+ - const: smwid
+ description: |
+ The standard Smwid extension for M-mode World ID control via the
+ mwid CSR as ratified at commit TBD ("TBD") of riscv-worlds.
+
+ - const: smwiddeleg
+ description: |
+ The standard Smwiddeleg extension for M-mode delegation of lower
+ privilege World ID control to S-mode via the mwiddeleg CSR, as
+ ratified at commit TBD ("TBD") of riscv-worlds.
+
- const: ssaia
description: |
The standard Ssaia supervisor-level extension for the advanced
@@ -262,6 +285,12 @@ properties:
ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
+ - const: sswid
+ description: |
+ The standard Sswid extension for S-mode control of lower
+ privilege World IDs via the slwid CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
- const: supm
description: |
The standard Supm extension for pointer masking support in user
@@ -924,6 +953,30 @@ properties:
then:
contains:
const: b
+ # Smlwidlist depends on Smwid and Smlwid
+ - if:
+ contains:
+ const: smlwidlist
+ then:
+ allOf:
+ - contains:
+ const: smwid
+ - contains:
+ const: smlwid
+ # Smwiddeleg depends on Smlwid
+ - if:
+ contains:
+ const: smwiddeleg
+ then:
+ contains:
+ const: smlwid
+ # Sswid depends on Smwiddeleg
+ - if:
+ contains:
+ const: sswid
+ then:
+ contains:
+ const: smwiddeleg
# Supm depends on Smnpm or Ssnpm
- if:
contains:
--
2.43.7
next prev parent reply other threads:[~2026-08-12 12:21 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-12 12:21 [RFC PATCH v3 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Yu-Chien Peter Lin
2026-08-12 12:21 ` Yu-Chien Peter Lin [this message]
2026-08-12 12:34 ` [RFC PATCH v3 1/3] dt-bindings: riscv: Add Worlds ISA extensions sashiko-bot
2026-08-12 12:21 ` [RFC PATCH v3 2/3] dt-bindings: riscv: Add Worlds per-hart properties Yu-Chien Peter Lin
2026-08-12 12:21 ` [RFC PATCH v3 3/3] dt-bindings: access-controllers: Add SiFive WorldGuard Checker Yu-Chien Peter Lin
2026-08-12 12:28 ` Yu-Chien Peter Lin
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