[RFC PATCH v3 2/3] dt-bindings: riscv: Add Worlds per-hart properties

[Yu-Chien Peter Lin <peter.lin@sifive.com>]

Add per-hart DT properties for the RISC-V Worlds architecture:
riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist. These
platform-defined values are primarily used by M-mode firmware
to configure World ID CSRs and restrict WID usage across
privilege levels.

Also add schema validation rules to enforce valid property
combinations based on the ISA extensions present.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
Changes v2->v3:
- Drop riscv,nworlds property
- Drop 'required' check for riscv,pmwid
---
 .../devicetree/bindings/riscv/cpus.yaml       | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 5feeb2203050..326b68398b90 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -39,6 +39,26 @@ allOf:
       properties:
         thead,vlenb: false
 
+  - if:
+      properties:
+        riscv,isa-extensions:
+          not:
+            contains:
+              const: smwid
+    then:
+      properties:
+        riscv,pmwidlist: false
+
+  - if:
+      properties:
+        riscv,isa-extensions:
+          not:
+            contains:
+              const: smlwid
+    then:
+      properties:
+        riscv,pmlwidlist: false
+
 properties:
   compatible:
     oneOf:
@@ -113,6 +133,30 @@ properties:
     description:
       The blocksize in bytes for the Zicboz cache operations.
 
+  riscv,pmlwidlist:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description:
+      Optional bitmask of WIDs available for S-mode and U-mode use on this
+      hart; each set bit N indicates WID N is available. Firmware may read
+      this to select platform authorized WIDs for lower-privilege modes.
+
+  riscv,pmwid:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      M-mode World ID (WID) for this hart, M-mode firmware may read this
+      property to identify the WID for M-mode. For a Worlds-aware platform
+      without any Worlds ISA implemented, this is the WID for all privilege
+      modes.
+    minimum: 0
+    maximum: 63
+
+  riscv,pmwidlist:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description:
+      Optional bitmask of WIDs available for M-mode use on this hart; each
+      set bit N indicates WID N is available. Firmware may read this to
+      select a platform authorized WID.
+
   thead,vlenb:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
-- 
2.43.7