[PATCH v2 0/3] iio: accel: adxl367: add INT2 interrupt pin support

[PATCH v2 0/3] iio: accel: adxl367: add INT2 interrupt pin support

[Antoniu Miclaus]

The ADXL367 exposes two independent interrupt output pins, INT1 and INT2,
each with its own event mapping register that shares an identical bit
layout. So far the driver has assumed the INT1 pin is the connected one.

This series adds an "interrupt-names" device tree property so a board can
describe which pin is wired, and teaches the driver to route the interrupt
mappings to the matching register. When no "interrupt-names" is present the
driver keeps defaulting to INT1, so existing device trees are unaffected.

Patch 1 refreshes the maintainer entries, since Cosmin's Analog Devices
address no longer exists.

Changes in v2:
- New patch 1/3 updating the binding maintainers field and MAINTAINERS.
- Propagate -EPROBE_DEFER from fwnode_irq_get_byname().
- Drop the redundant irq return; the helper now only selects the INT map
  register.
- Picked up Rob's Reviewed-by on the interrupt-names binding patch.

Antoniu Miclaus (3):
  iio: accel: adxl367: update maintainer entries
  dt-bindings: iio: accel: adi,adxl367: add interrupt-names
  iio: accel: adxl367: add support for INT2 interrupt pin

 .../bindings/iio/accel/adi,adxl367.yaml       | 13 ++++++-
 MAINTAINERS                                   |  1 +
 drivers/iio/accel/adxl367.c                   | 39 +++++++++++++++++--
 3 files changed, 48 insertions(+), 5 deletions(-)


base-commit: 0b5e142ced4bcf20532da051934bd694d1bbd470
-- 
2.43.0

[PATCH v2 1/3] iio: accel: adxl367: update maintainer entries

[Antoniu Miclaus]

Cosmin's Analog Devices address is no longer valid, leaving the ADXL367
binding without a reachable maintainer. Take over maintainership of the
binding and add myself to the MAINTAINERS entry alongside Marcelo.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
Changes in v2:
- New patch.

 Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml | 2 +-
 MAINTAINERS                                                  | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml
index f10d98d34cb8..29689bc38b90 100644
--- a/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml
+++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Analog Devices ADXL367 3-Axis Digital Accelerometer
 
 maintainers:
-  - Cosmin Tanislav <cosmin.tanislav@analog.com>
+  - Antoniu Miclaus <antoniu.miclaus@analog.com>
 
 description: |
   The ADXL367 is an ultralow power, 3-axis MEMS accelerometer.
diff --git a/MAINTAINERS b/MAINTAINERS
index 7077ed7c9efe..69e41b262a6d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -641,6 +641,7 @@ F:	drivers/iio/accel/adxl355_spi.c
 
 ADXL367 THREE-AXIS DIGITAL ACCELEROMETER DRIVER
 M:	Marcelo Schmitt <marcelo.schmitt@analog.com>
+M:	Antoniu Miclaus <antoniu.miclaus@analog.com>
 L:	linux-iio@vger.kernel.org
 S:	Supported
 W:	https://ez.analog.com/linux-software-drivers
-- 
2.43.0

[PATCH v2 2/3] dt-bindings: iio: accel: adi,adxl367: add interrupt-names

[Antoniu Miclaus]

The ADXL367 has two independent interrupt output pins, INT1 and INT2,
either of which may be wired to the host. Allow the interrupt line that
is connected to be described by adding an optional interrupt-names
property accepting "INT1" and/or "INT2", and permit a second interrupt
entry. interrupt-names is kept optional so existing device trees that
only specify a bare interrupts property remain valid.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
Changes in v2:
- No changes.

 .../devicetree/bindings/iio/accel/adi,adxl367.yaml    | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml
index 29689bc38b90..115170eac058 100644
--- a/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml
+++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml
@@ -33,7 +33,14 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  interrupt-names:
+    minItems: 1
+    items:
+      - enum: [INT1, INT2]
+      - const: INT2
 
   vdd-supply: true
   vddio-supply: true
@@ -61,6 +68,7 @@ examples:
         reg = <0x53>;
         interrupt-parent = <&gpio>;
         interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+        interrupt-names = "INT1";
       };
     };
   - |
@@ -76,5 +84,6 @@ examples:
         spi-max-frequency = <1000000>;
         interrupt-parent = <&gpio>;
         interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+        interrupt-names = "INT1";
       };
     };
-- 
2.43.0

[PATCH v2 3/3] iio: accel: adxl367: add support for INT2 interrupt pin

[Antoniu Miclaus]

The ADXL367 provides two independent interrupt output pins, INT1 and
INT2, each with its own event mapping register (INTMAP1_LOWER at 0x2A
and INTMAP2_LOWER at 0x2B) sharing an identical bit layout. Until now
the driver hardcoded INT1 for all interrupt mappings, so a board that
routes only INT2 to the host could never receive activity, inactivity
or FIFO watermark interrupts.

Determine the connected pin from the interrupt-names device tree
property using fwnode_irq_get_byname(), and route the interrupt
mappings to the matching register. When no interrupt-names are present,
default to INT1 to preserve the existing behaviour.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
Changes in v2:
- Propagate -EPROBE_DEFER from fwnode_irq_get_byname().
- Drop the redundant irq return; the helper now only selects the INT map
  register.

 drivers/iio/accel/adxl367.c | 39 ++++++++++++++++++++++++++++++++++---
 1 file changed, 36 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c
index 8c3de11a10a3..df385740b17b 100644
--- a/drivers/iio/accel/adxl367.c
+++ b/drivers/iio/accel/adxl367.c
@@ -13,6 +13,7 @@
 #include <linux/iio/sysfs.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/property.h>
 #include <linux/regmap.h>
 #include <linux/regulator/consumer.h>
 #include <linux/unaligned.h>
@@ -81,6 +82,7 @@
 #define ADXL367_SAMPLES_L_MASK		GENMASK(7, 0)
 
 #define ADXL367_REG_INT1_MAP		0x2A
+#define ADXL367_REG_INT2_MAP		0x2B
 #define ADXL367_INT_INACT_MASK		BIT(5)
 #define ADXL367_INT_ACT_MASK		BIT(4)
 #define ADXL367_INT_FIFO_WATERMARK_MASK	BIT(2)
@@ -168,6 +170,8 @@ struct adxl367_state {
 	enum adxl367_odr	odr;
 	enum adxl367_range	range;
 
+	u8		int_map_reg;
+
 	unsigned int	act_threshold;
 	unsigned int	act_time_ms;
 	unsigned int	inact_threshold;
@@ -366,7 +370,7 @@ static int adxl367_set_act_interrupt_en(struct adxl367_state *st,
 {
 	unsigned int mask = adxl367_act_int_mask_tbl[act];
 
-	return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
+	return regmap_update_bits(st->regmap, st->int_map_reg,
 				  mask, en ? mask : 0);
 }
 
@@ -378,7 +382,7 @@ static int adxl367_get_act_interrupt_en(struct adxl367_state *st,
 	unsigned int val;
 	int ret;
 
-	ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);
+	ret = regmap_read(st->regmap, st->int_map_reg, &val);
 	if (ret)
 		return ret;
 
@@ -401,7 +405,7 @@ static int adxl367_set_act_en(struct adxl367_state *st,
 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,
 						   bool en)
 {
-	return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
+	return regmap_update_bits(st->regmap, st->int_map_reg,
 				  ADXL367_INT_FIFO_WATERMARK_MASK,
 				  en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0);
 }
@@ -1426,6 +1430,31 @@ static int adxl367_setup(struct adxl367_state *st)
 	return adxl367_set_measure_en(st, true);
 }
 
+static int adxl367_set_int_map_reg(struct adxl367_state *st)
+{
+	int irq;
+
+	irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT1");
+	if (irq == -EPROBE_DEFER)
+		return irq;
+	if (irq > 0) {
+		st->int_map_reg = ADXL367_REG_INT1_MAP;
+		return 0;
+	}
+
+	irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT2");
+	if (irq == -EPROBE_DEFER)
+		return irq;
+	if (irq > 0) {
+		st->int_map_reg = ADXL367_REG_INT2_MAP;
+		return 0;
+	}
+
+	/* No interrupt-names: default to INT1 for backwards compatibility. */
+	st->int_map_reg = ADXL367_REG_INT1_MAP;
+	return 0;
+}
+
 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
 		  void *context, struct regmap *regmap, int irq)
 {
@@ -1482,6 +1511,10 @@ int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
 	if (ret)
 		return ret;
 
+	ret = adxl367_set_int_map_reg(st);
+	if (ret)
+		return dev_err_probe(st->dev, ret, "Failed to get interrupt\n");
+
 	ret = devm_request_threaded_irq(st->dev, irq, NULL,
 					adxl367_irq_handler, IRQF_ONESHOT,
 					indio_dev->name, indio_dev);
-- 
2.43.0

Re: [PATCH v2 3/3] iio: accel: adxl367: add support for INT2 interrupt pin

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The driver configures the interrupt map register based on a hardcoded name priority, but ignores the corresponding IRQ line and registers the default `irq` parameter, risking an IRQ routing mismatch.
--

--- Patch [3]: [PATCH v2 3/3] iio: accel: adxl367: add support for INT2 interrupt pin ---
commit 89ea1f01faa6ff074e5199721996b317c618f006
Author: Antoniu Miclaus <antoniu.miclaus@analog.com>

iio: accel: adxl367: add support for INT2 interrupt pin

The ADXL367 provides two independent interrupt output pins, INT1 and
INT2, each with its own event mapping register. This commit updates the
driver to determine the connected pin from the interrupt-names device tree
property and routes the interrupt mappings to the matching register.

> diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c
> index 8c3de11a10a37..df385740b17b5 100644
> --- a/drivers/iio/accel/adxl367.c
> +++ b/drivers/iio/accel/adxl367.c

[ ... ]

> @@ -1426,6 +1430,31 @@ static int adxl367_setup(struct adxl367_state *st)
>  	return adxl367_set_measure_en(st, true);
>  }
>  
> +static int adxl367_set_int_map_reg(struct adxl367_state *st)
> +{
> +	int irq;
> +
> +	irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT1");
> +	if (irq == -EPROBE_DEFER)
> +		return irq;
> +	if (irq > 0) {
> +		st->int_map_reg = ADXL367_REG_INT1_MAP;
> +		return 0;
> +	}
> +
> +	irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT2");
> +	if (irq == -EPROBE_DEFER)
> +		return irq;
> +	if (irq > 0) {
> +		st->int_map_reg = ADXL367_REG_INT2_MAP;
> +		return 0;
> +	}
> +
> +	/* No interrupt-names: default to INT1 for backwards compatibility. */
> +	st->int_map_reg = ADXL367_REG_INT1_MAP;
> +	return 0;
> +}
> +

[ ... ]

> @@ -1482,6 +1511,10 @@ int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
>  	if (ret)
>  		return ret;
>  
> +	ret = adxl367_set_int_map_reg(st);
> +	if (ret)
> +		return dev_err_probe(st->dev, ret, "Failed to get interrupt\n");
> +
>  	ret = devm_request_threaded_irq(st->dev, irq, NULL,
>  					adxl367_irq_handler, IRQF_ONESHOT,
>  					indio_dev->name, indio_dev);

[Severity: High]
Could this cause a mismatch between the interrupt map register and the
requested irq line?

If a device tree specifies both interrupts but INT2 is listed first
(index 0), the SPI/I2C core passes the INT2 irq as the irq parameter to
adxl367_probe().

Meanwhile, adxl367_set_int_map_reg() checks INT1 first, configures the
sensor to route interrupts to the INT1 pin, and discards the retrieved
irq number.

Then devm_request_threaded_irq() registers the handler on the original irq
parameter (INT2). Does this result in the device signaling on INT1 while
the OS listens on INT2?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260813081452.4289-1-antoniu.miclaus@analog.com?part=3