[PATCH 0/2] PCI: introduce TC9564 misc driver

[PATCH 0/2] PCI: introduce TC9564 misc driver

[Alex Elder]

The Toshiba TC9564 is specialized SoC that implements a PCIe switch as
well as an Ethernet AVB/TSN bridge.  It also implements other functions,
including a reset and clock controller, an address translation unit, and
a few other devices.  PCIe BARs provide access to registers that manage
these IP blocks, and the SoC is modeled using a PCI endpoint bus in
devicetree.  This allows the IP blocks to be bound to platform drivers
using MMIO through the PCI BARs.

This series introduces the simple PCI driver necessary to implement the
PCI endpoint bus.  It enables the device, enables master access, and
then scans the devicetree subnodes to discover any devices defined
within the endpoint buses.

					-Alex

Note: to work correctly, this series depends on this:
  https://lore.kernel.org/lkml/20260813220717.1394644-1-elder@riscstar.com/

Alex Elder (2):
  dt-bindings: misc: introduce pci1179,0220.yaml
  misc: tc9564: introduce base PCI driver

 .../bindings/misc/pci1179,0220.yaml           | 150 ++++++++++++++++++
 MAINTAINERS                                   |   7 +
 drivers/misc/Kconfig                          |  10 ++
 drivers/misc/Makefile                         |   1 +
 drivers/misc/tc9564-pci.c                     |  89 +++++++++++
 drivers/pci/quirks.c                          |   1 +
 6 files changed, 258 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/pci1179,0220.yaml
 create mode 100644 drivers/misc/tc9564-pci.c


base-commit: 5e6de6a2b522f659defacb1551d0465ba6ce13cf
-- 
2.53.0

[PATCH 1/2] dt-bindings: misc: introduce pci1179,0220.yaml

[Alex Elder]

Define the binding for the Toshiba TC9564 PCI endpoint function device.
The third downstream PCIe switch port within this chip has an embedded
PCIe controller, and that implements two of these PCIe functions.

Signed-off-by: Daniel Thompson <daniel@riscstar.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
---
 .../bindings/misc/pci1179,0220.yaml           | 150 ++++++++++++++++++
 MAINTAINERS                                   |   6 +
 2 files changed, 156 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/pci1179,0220.yaml

diff --git a/Documentation/devicetree/bindings/misc/pci1179,0220.yaml b/Documentation/devicetree/bindings/misc/pci1179,0220.yaml
new file mode 100644
index 0000000000000..30a76f377eec8
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/pci1179,0220.yaml
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/pci1179,0220.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba TC9564 internal PCI endpoint function
+
+maintainers:
+  - Alex Elder <elder@kernel.org>
+  - Daniel Thompson <danielt@kernel.org>
+
+description: >
+  The Toshiba TC9564 is specialized SoC that implements a PCIe switch
+  as well as an Ethernet AVB/TSN bridge.  In addition to these, the SoC
+  implements other functions, including a reset and clock controller,
+  an address translation unit, and a few other devices.
+
+  The PCI switch has three downstream ports.  The first two are exposed
+  externally, while the third is used by an internal PCIe endpoint.  The
+  internal endpoint implements two PCIe functions, and attached to each
+  of these is a 10 Gbps capable Synopsys Ethernet controller and an
+  interrupt controller that converts internal "wired" interrupts into
+  MSIs delivered to the host.
+
+  PCIe BARs provide access to registers that manage almost all IP blocks.
+  The SoC is modeled using a PCI endpoint bus.  The IP blocks are bound
+  to platform drivers that access the hardware using MMIO through the
+  PCI BARs.
+
+          ------------------------------------
+          |               Host               |
+          -----........---------------...-----
+              |        |             |   |
+              |  PCIe  |             |I2C|
+              |        |             |   |
+    ----------+........+-------------+...+---------------------------
+    |         |upstream|          |          |     ---------------- |
+    | Toshiba | Port 0 |          |          +-----+ PCIe pwrctrl | |
+    | TC9564  ----++----          |   I2C    |     ---------------- |
+    |  SoC        ||              |controller|     ---------------- |
+    |             ||              |          +-----+     GPIO     | |
+    |             ||              |          |     |  controller  | |
+    |       ------++------        ------------     ---------------- |
+    |       |     US     |                                          |
+    |       |            |    ------------------------------------- |
+    |       |         DS3+====+          downstream port 3        | |
+    |       |            |    |-----------------------------------| |
+    |       |    PCIe    |    |       embedded PCIe endpoint      | |
+    |       |            |    |~~~~~~~~~~~~~~~~~+~~~~~~~~~~~~~~~~~| |
+    |       |   Switch   |    | PCIe function 0 | PCIe function 1 | |
+    |       |            |    |-----------------+-----------------| |
+    |       |            |    |  BAR  | |  BAR  |         |  BAR  | |
+    |       |            |    |   0   | |   4   |         |   4   | |
+    |       | DS1    DS2 |    ----.---- ----.----         ----.---- |
+    |       --++------++--        :      ...:                 :...  |
+    |         ||      ||          :      :  :   -------       :  |  |
+    |         ||      ||   -------.---  -.- :...|clock|       : -.- |
+    |         ||      ||   |translate|  |M| :   -------       : |M| |
+    |         ||      ||   -----------  |S| :                 : |S| |
+    |         ||      ||                |I| :   -------       : |I| |
+    |         ||      ||                |G| :...|reset|       : |G| |
+    |         ||      ||                |E| :   -------       : |E| |
+    | --------++--  --++--------        |N| :                 : |N| |
+    | |downstream|  |downstream|      ------.----       ------.---- |
+    | |  port 1  |  |  port 2  |      | XGMAC 0 |       | XGMAC 1 | |
+    --+..........+--+..........+-------+.......+---------+.....+-----
+                                      |       |          |     |
+                                      |USXGMII|          |SGMII|
+                                      |       |          |     |
+                                    ---+.....+---      --+.....+--
+                                    |  Ethernet |      | Ethernet|
+                                    |    PHY    |      |   PHY   |
+                                    -------------      -----------
+
+allOf:
+  - $ref: /schemas/pci/pci-ep-bus.yaml
+
+properties:
+  compatible:
+    const: pci1179,0220 # Toshiba TC96564 (a.k.a. Qualcomm QPS615)
+
+  reg:
+    maxItems: 1
+    description: PCI Bus/Device/Function config space address
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - '#address-cells'
+  - '#size-cells'
+  - ranges
+
+examples:
+  - |
+    pcie@0 {
+        reg = <0x0  0x0>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        ranges = <0x83000000 0x0 0x0  0x0  0x0 0x1fd00000>;
+
+        pci@0,0 {
+            compatible = "pci1179,0220";
+            reg = <0x0 0x0 0x0 0x0 0x0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            /* Ranges will be updated dynamically */
+            ranges = <0x0 0x0 0x0  0x83000000 0x0 0x0  0x0 0x4000>,
+                     <0x2 0x0 0x0  0x83000000 0x0 0x0  0x0 0x80000>,
+                     <0x4 0x0 0x0  0x83000000 0x0 0x0  0x0 0x200000>;
+
+            pci-ep-bus@0 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /* Map 0x0-0x3fff to BAR 0 */
+                ranges = <0x0  0x0 0x0 0x0  0x4000>;
+            };
+
+            pci-ep-bus@4 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /* Map 0x0-0x1fffff to BAR 4 */
+                ranges = <0x0  0x4 0x0 0x0  0x200000>;
+            };
+        };
+
+        pci@0,1 {
+            compatible = "pci1179,0220";
+            reg = <0x100 0x0 0x0 0x0 0x0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            /* Ranges will be updated dynamically */
+            ranges = <0x0 0x0 0x0  0x83000100 0x0 0x0  0x0 0x4000>,
+                     <0x2 0x0 0x0  0x83000100 0x0 0x0  0x0 0x80000>,
+                     <0x4 0x0 0x0  0x83000100 0x0 0x0  0x0 0x200000>;
+
+            pci-ep-bus@4 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /* Map 0x0-0x1fffff to BAR 4 */
+                ranges = <0x0  0x4 0x0 0x0  0x200000>;
+            };
+        };
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 15c7dc516f7cf..7b7966ad3dea5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -27615,6 +27615,12 @@ F:	Documentation/devicetree/bindings/media/i2c/toshiba,tc358743.txt
 F:	drivers/media/i2c/tc358743*
 F:	include/media/i2c/tc358743.h
 
+TOSHIBA TC9564 PCI DRIVER
+M:	Alex Elder <elder@kernel.org>
+M:	Daniel Thompson <danielt@kernel.org>
+S:	Maintained
+F:	Documentation/devicetree/bindings/misc/pci1179,0220.yaml
+
 TOSHIBA WMI HOTKEYS DRIVER
 M:	Azael Avalos <coproscefalo@gmail.com>
 L:	platform-driver-x86@vger.kernel.org
-- 
2.53.0

Re: [PATCH 1/2] dt-bindings: misc: introduce pci1179,0220.yaml

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The example DT nodes map multiple PCI BARs to the exact same parent physical address, and define unused BARs that contradict the hardware diagram.
- [Low] Typographical error in the compatible string comment.
--

--- Patch [1]: [PATCH 1/2] dt-bindings: misc: introduce pci1179,0220.yaml ---
commit ee5f64080011b047dd81e1bbdc568f784c09b77f
Author: Alex Elder <elder@riscstar.com>

dt-bindings: misc: introduce pci1179,0220.yaml

Define the binding for the Toshiba TC9564 PCI endpoint function device.
The third downstream PCIe switch port within this chip has an embedded
PCIe controller, and that implements two of these PCIe functions.

> diff --git a/Documentation/devicetree/bindings/misc/pci1179,0220.yaml b/Documentation/devicetree/bindings/misc/pci1179,0220.yaml
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/pci1179,0220.yaml
[ ... ]
> +properties:
> +  compatible:
> +    const: pci1179,0220 # Toshiba TC96564 (a.k.a. Qualcomm QPS615)

[Severity: Low]
This isn't a bug, but there's a typo in this comment. It says TC96564 instead
of TC9564.

[ ... ]
> +        pci@0,0 {
> +            compatible = "pci1179,0220";
> +            reg = <0x0 0x0 0x0 0x0 0x0>;
> +            #address-cells = <3>;
> +            #size-cells = <2>;
> +            /* Ranges will be updated dynamically */
> +            ranges = <0x0 0x0 0x0  0x83000000 0x0 0x0  0x0 0x4000>,
> +                     <0x2 0x0 0x0  0x83000000 0x0 0x0  0x0 0x80000>,
> +                     <0x4 0x0 0x0  0x83000000 0x0 0x0  0x0 0x200000>;

[Severity: Low]
Are these example ranges accurate for the hardware? The mappings configure
BAR 0, BAR 2, and BAR 4 to use the identical parent physical address 
(0x83000000), which would result in overlapping memory regions.

Additionally, the hardware diagram in the binding description indicates
BAR 2 is not present, but it is configured in this example.

[ ... ]
> +        pci@0,1 {
> +            compatible = "pci1179,0220";
> +            reg = <0x100 0x0 0x0 0x0 0x0>;
> +            #address-cells = <3>;
> +            #size-cells = <2>;
> +            /* Ranges will be updated dynamically */
> +            ranges = <0x0 0x0 0x0  0x83000100 0x0 0x0  0x0 0x4000>,
> +                     <0x2 0x0 0x0  0x83000100 0x0 0x0  0x0 0x80000>,
> +                     <0x4 0x0 0x0  0x83000100 0x0 0x0  0x0 0x200000>;

[Severity: Low]
Do these ranges match the hardware design for Function 1? The example maps
BAR 0 and BAR 2 here, but the hardware diagram indicates Function 1 only
uses BAR 4.

These mappings also map to the same parent physical address (0x83000100),
causing overlapping memory regions similar to the previous node.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260813222943.1655453-1-elder@riscstar.com?part=1

Re: [PATCH 1/2] dt-bindings: misc: introduce pci1179,0220.yaml

[Krzysztof Kozlowski]

On Thu, Aug 13, 2026 at 05:29:41PM -0500, Alex Elder wrote:
> Define the binding for the Toshiba TC9564 PCI endpoint function device.
> The third downstream PCIe switch port within this chip has an embedded
> PCIe controller, and that implements two of these PCIe functions.
> 
> Signed-off-by: Daniel Thompson <daniel@riscstar.com>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
>  .../bindings/misc/pci1179,0220.yaml           | 150 ++++++++++++++++++
>  MAINTAINERS                                   |   6 +
>  2 files changed, 156 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/misc/pci1179,0220.yaml
>

There are no properties in the binding except standard PCIe ones, so why
do you need it in DT in the first place? We do not describe PCI devices
in DT by default, so you are doing something unusual. Commit msg should
explain that.

Best regards,
Krzysztof

[PATCH 2/2] misc: tc9564: introduce base PCI driver

[Alex Elder]

The Toshiba TC9564 is small and highly-specialized SoC that implements
a PCIe switch as well as an Ethernet AVB/TSN bridge.  In addition to
these, the SoC implements other functions, including a reset and clock
controller, an address translation unit, and a few other devices.  PCIe
BARs provide access to registers that manage these IP blocks, and the
SoC is modeled using a PCI endpoint bus in devicetree.  This allows the
IP blocks to be bound to platform drivers using MMIO through the PCI BARs.

Create a new PCI driver under drivers/misc that binds with the embedded
PCI endpoint functions within the TC9564 SoC.  Because these functions
will use devicetree pci-ep-bus to provide access to other IP blocks
within the TC9564 chip, the main purpose of this driver is to do basic
PCI initialization, then call of_platform_default_populate() to scan for
the any endpoint bus children, and probe all devices defined therein.

Because we're using pci-ep-bus, we need to use the PCI quirks mechanism
to have of_pci_make_dev_node() be called for each endpoint device in
pci_bus_add_device() (via pci_fixup_device(pci_fixup_final, dev)).

Signed-off-by: Daniel Thompson <daniel@riscstar.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
---
 MAINTAINERS               |  1 +
 drivers/misc/Kconfig      | 10 +++++
 drivers/misc/Makefile     |  1 +
 drivers/misc/tc9564-pci.c | 89 +++++++++++++++++++++++++++++++++++++++
 drivers/pci/quirks.c      |  1 +
 5 files changed, 102 insertions(+)
 create mode 100644 drivers/misc/tc9564-pci.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 7b7966ad3dea5..125fa60122c4e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -27620,6 +27620,7 @@ M:	Alex Elder <elder@kernel.org>
 M:	Daniel Thompson <danielt@kernel.org>
 S:	Maintained
 F:	Documentation/devicetree/bindings/misc/pci1179,0220.yaml
+F:	drivers/misc/tc9564-pci.c
 
 TOSHIBA WMI HOTKEYS DRIVER
 M:	Azael Avalos <coproscefalo@gmail.com>
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 7364931dad3a1..91950d2928f07 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -568,6 +568,16 @@ config MCHP_LAN966X_PCI
 	    - lan966x-miim (MDIO_MSCC_MIIM)
 	    - lan966x-switch (LAN966X_SWITCH)
 
+config TC9564_PCI
+	tristate "Toshiba TC9564 PCI function support"
+	depends on PCI
+	select REGMAP_MMIO
+	help
+	  This enables support for the two PCI functions implemented by
+	  the embedded PCIe endpoint in the Toshiba TC9564 SoC.  This
+	  driver uses a pci-ep-bus node in devicetree to provide MMIO
+	  access to other SoC devices through PCI function BARs.
+
 source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index e8d8d5d88c0df..7cc3d615d37a4 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -71,3 +71,4 @@ obj-y				+= keba/
 obj-y				+= amd-sbi/
 obj-$(CONFIG_MISC_RP1)		+= rp1/
 obj-$(CONFIG_INTEL_SSEI)	+= issei/
+obj-$(CONFIG_TC9564_PCI)	+= tc9564-pci.o
diff --git a/drivers/misc/tc9564-pci.c b/drivers/misc/tc9564-pci.c
new file mode 100644
index 0000000000000..d3ffcac1c522f
--- /dev/null
+++ b/drivers/misc/tc9564-pci.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright (C) 2026 by RISCstar Solutions Corporation.  All rights reserved.
+ */
+
+/*
+ * The Toshiba TC9564 implements a PCIe Gen 3 switch that connects an
+ * upstream x4 port to three downstream PCIe ports.  Two of the downstream
+ * ports are external, and the third is internal, implementing a PCIe
+ * endpoint with implements two PCIe functions.  Each PCIe function drives
+ * a Synopsys XGMAC Ethernet interface capable of 10 Gbps operation.
+ *
+ * The TC9564 implements other functionality, including an embedded MCU,
+ * a UART, a GPIO controller, a reset controller, a clock controller, and
+ * interrupt handling.  These features are separate from (and in some
+ * cases used by) both Ethernet XGMACs.  Each Ethernet MAC must be
+ * attached to a working PHY for it to be functional, and for this
+ * reason either of them (or both!) might not be usable/used.
+ *
+ * This PCI driver binds to the Toshiba TC9564 (physical) PCI function
+ * (VID 0x1179, DID 0x0220).
+ */
+
+#include <linux/device.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+
+#define DRIVER_NAME "tc9564-pci"
+
+static int
+tc9564_function_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np;
+	int ret;
+
+	/* Despite being a PCI device, we require devicetree */
+	np = dev_of_node(dev);
+	if (!np)
+		return dev_err_probe(dev, -EINVAL, "no devicetree node\n");
+
+	ret = pcim_enable_device(pdev);
+	if (ret)
+		return ret;
+
+	pci_set_master(pdev);
+
+	/* Scan for pci-ep-bus nodes and probe their sub-devices */
+	ret = of_platform_default_populate(np, NULL, dev);
+	if (ret)
+		goto err_clear_master;
+
+	return 0;
+
+err_clear_master:
+	pci_clear_master(pdev);
+
+	return dev_err_probe(dev, ret, "failed to populate platform bus\n");
+}
+
+static void tc9564_function_remove(struct pci_dev *pdev)
+{
+	of_platform_depopulate(&pdev->dev);
+	pci_clear_master(pdev);
+}
+
+static const struct pci_device_id tc9564_function_id_table[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA, 0x0220), },
+	{ },
+};
+MODULE_DEVICE_TABLE(pci, tc9564_function_id_table);
+
+static struct pci_driver tc9564_function_driver = {
+	.name		= DRIVER_NAME,
+	.id_table	= tc9564_function_id_table,
+	.probe		= tc9564_function_probe,
+	.remove		= tc9564_function_remove,
+	.driver		= {
+		.name		= DRIVER_NAME,
+		.owner		= THIS_MODULE,
+	},
+};
+module_pci_driver(tc9564_function_driver);
+
+MODULE_DESCRIPTION("Toshiba TC9564 PCIe Embedded Function Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 6501c949c5b76..b484f1b1d0e71 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -6388,6 +6388,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA, 0x0220, of_pci_make_dev_node);
 
 /*
  * Devices known to require a longer delay before first config space access
-- 
2.53.0

Re: [PATCH 2/2] misc: tc9564: introduce base PCI driver

[Greg KH]

On Thu, Aug 13, 2026 at 05:29:42PM -0500, Alex Elder wrote:
> +#define DRIVER_NAME "tc9564-pci"

What about just using KBUILD_MODNAME?

> +static int
> +tc9564_function_probe(struct pci_dev *pdev, const struct pci_device_id *id)

But wow, this is a tiny driver, feels odd to have it in misc/ but ok, if
you think it should be here...

thanks,

greg k-h

Re: [PATCH 2/2] misc: tc9564: introduce base PCI driver

[Arnd Bergmann]

On Fri, Aug 14, 2026, at 03:11, Greg KH wrote:
> On Thu, Aug 13, 2026 at 05:29:42PM -0500, Alex Elder wrote:
>> +#define DRIVER_NAME "tc9564-pci"
>
> What about just using KBUILD_MODNAME?
>
>> +static int
>> +tc9564_function_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>
> But wow, this is a tiny driver, feels odd to have it in misc/ but ok, if
> you think it should be here...

We have drivers/misc/rp1/ and drivers/misc/lan966x_pci*.c with similar
functionality, so at least there is precedence for putting them here.

From the old days, we still have drivers/mfd/sm501.c, drivers/mfd/cs5535-mfd.c,
and a few others that open-code the on-chip components as mfd cels
instead of using devicetree description.

At some point, we should think about grouping them into a separate
subdirectory.

     Arnd

Re: [PATCH 2/2] misc: tc9564: introduce base PCI driver

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing PCI IRQ vector allocation prevents MSI/MSI-X usage for high-speed child devices.
--

--- Patch [2]: [PATCH 2/2] misc: tc9564: introduce base PCI driver ---
commit e66bfe4041c21f48829a22eb54cde73756806870
Author: Alex Elder <elder@riscstar.com>
misc: tc9564: introduce base PCI driver

This commit introduces a base PCI driver for the Toshiba TC9564 SoC which
implements a PCIe switch and Ethernet AVB/TSN bridge. The driver binds to the
embedded PCI endpoint functions, performs basic PCI initialization, and uses
devicetree to populate any endpoint bus children.

[ ... ]

> diff --git a/drivers/misc/tc9564-pci.c b/drivers/misc/tc9564-pci.c
> new file mode 100644
> index 0000000000000..d3ffcac1c522f
> --- /dev/null
> +++ b/drivers/misc/tc9564-pci.c

[ ... ]

> +static int
> +tc9564_function_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np;
> +	int ret;
> +
> +	/* Despite being a PCI device, we require devicetree */
> +	np = dev_of_node(dev);
> +	if (!np)
> +		return dev_err_probe(dev, -EINVAL, "no devicetree node\n");
> +
> +	ret = pcim_enable_device(pdev);
> +	if (ret)
> +		return ret;
> +
> +	pci_set_master(pdev);
> +
> +	/* Scan for pci-ep-bus nodes and probe their sub-devices */

[Severity: High]
Does this setup sequence omit PCI IRQ vector allocation? 

Without calling pci_alloc_irq_vectors() in tc9564_function_probe() before
populating the child devices, the Linux PCI core won't configure the device's
MSI/MSI-X capabilities with host addresses and data payloads. 

Since child platform drivers cannot safely allocate PCI IRQ vectors on behalf
of their parent PCI device, will the high-speed child devices (like the 10Gbps
Ethernet XGMACs) be forced to share a single legacy INTx interrupt, or fail
entirely if the host platform does not support legacy PCI interrupts?

> +	ret = of_platform_default_populate(np, NULL, dev);
> +	if (ret)
> +		goto err_clear_master;
> +
> +	return 0;
> +
> +err_clear_master:
> +	pci_clear_master(pdev);
> +
> +	return dev_err_probe(dev, ret, "failed to populate platform bus\n");
> +}

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260813222943.1655453-1-elder@riscstar.com?part=2

Re: [PATCH 2/2] misc: tc9564: introduce base PCI driver

[Krzysztof Kozlowski]

On Thu, Aug 13, 2026 at 05:29:42PM -0500, Alex Elder wrote:
> +static struct pci_driver tc9564_function_driver = {
> +	.name		= DRIVER_NAME,
> +	.id_table	= tc9564_function_id_table,
> +	.probe		= tc9564_function_probe,
> +	.remove		= tc9564_function_remove,
> +	.driver		= {
> +		.name		= DRIVER_NAME,
> +		.owner		= THIS_MODULE,

You just copied some old driver. Why do you need this?

> +	},
> +};
> +module_pci_driver(tc9564_function_driver);
> +
> +MODULE_DESCRIPTION("Toshiba TC9564 PCIe Embedded Function Driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 6501c949c5b76..b484f1b1d0e71 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -6388,6 +6388,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA, 0x0220, of_pci_make_dev_node);
>  
>  /*
>   * Devices known to require a longer delay before first config space access
> -- 
> 2.53.0
>