From: Long Zhao via B4 Relay <devnull+longzhao.ambarella.com@kernel.org>
To: Arnd Bergmann <arnd@arndb.de>,
Krzysztof Kozlowski <krzk@kernel.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org,
linux-kernel@vger.kernel.org, Brian Masney <bmasney@redhat.com>,
Lee Jones <lee@kernel.org>,
mfd@lists.linux.dev, Long Zhao <zl020895@163.com>,
Long Zhao <longzhao@ambarella.com>
Subject: [PATCH v5 04/12] dt-bindings: pinctrl: add Ambarella CV75 pinctrl
Date: Tue, 18 Aug 2026 18:31:18 +0800 [thread overview]
Message-ID: <20260818-cv75-v5-v5-4-7bbb12f0360f@ambarella.com> (raw)
In-Reply-To: <20260818-cv75-v5-v5-0-7bbb12f0360f@ambarella.com>
From: Long Zhao <longzhao@ambarella.com>
Document the CV75 pin controller binding using generic function and
groups properties for pinmux configuration.
Signed-off-by: Long Zhao <longzhao@ambarella.com>
---
.../bindings/pinctrl/ambarella,cv75-pinctrl.yaml | 239 +++++++++++++++++++++
1 file changed, 239 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml
new file mode 100644
index 000000000000..34054bc56c3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml
@@ -0,0 +1,239 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/ambarella,cv75-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ambarella CV75 Pin Controller
+
+maintainers:
+ - Long Zhao <longzhao@ambarella.com>
+
+description:
+ The Ambarella CV75 pin controller configures pin multiplexing, bias and
+ drive strength for the main GPIO banks. Pin groups and their mux settings
+ are defined by the pin controller driver and selected by function and group
+ names.
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+properties:
+ compatible:
+ const: ambarella,cv75-pinctrl
+
+ reg:
+ maxItems: 1
+ description: IOMUX registers
+
+ ambarella,drive-strength-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: RCT syscon containing the drive-strength registers.
+
+ ambarella,pull-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Secure scratchpad syscon containing the pull registers.
+
+patternProperties:
+ "^[a-z0-9-]+-pins$":
+ type: object
+ allOf:
+ - $ref: pinmux-node.yaml#
+ - $ref: pincfg-node.yaml#
+ additionalProperties: false
+
+ properties:
+ function:
+ enum:
+ - can0
+ - can1
+ - clk_au
+ - dmic0
+ - enet0
+ - hsync0
+ - hsync1
+ - i2c0
+ - i2c1
+ - i2c2
+ - i2c3
+ - i2cs
+ - i2s0
+ - i2s1
+ - ir
+ - pwm0
+ - pwm1
+ - pwm2
+ - pwm3
+ - pwm4
+ - pwm5
+ - pwm6
+ - pwm7
+ - pwm8
+ - pwm9
+ - pwm10
+ - pwm11
+ - sdmmc0
+ - sdmmc1
+ - snand
+ - spi0
+ - spi1
+ - spi2
+ - spi3
+ - spi_slave
+ - spinor
+ - uart0
+ - uart1
+ - uart2
+ - uart3
+ - uart4
+ - vin_master_sync
+ - vsync0
+ - vsync1
+ - vsync2
+ - vsync3
+ - wdt
+
+ groups:
+ items:
+ enum:
+ - can0
+ - can1
+ - clk_au
+ - dmic0
+ - enet_2nd_ref_clk_a
+ - enet_2nd_ref_clk_b
+ - enet_ext_osc_clk
+ - enet0_ptp_pps_o
+ - hsync0
+ - hsync1
+ - i2c0_a
+ - i2c0_b
+ - i2c1_a
+ - i2c1_b
+ - i2c2
+ - i2c3_a
+ - i2c3_b
+ - i2c3_c
+ - i2cs_a
+ - i2cs_b
+ - i2cs_c
+ - i2cs_d
+ - i2s0
+ - i2s1
+ - ir
+ - pwm0
+ - pwm1
+ - pwm2
+ - pwm3
+ - pwm4_a
+ - pwm4_b
+ - pwm5_a
+ - pwm5_b
+ - pwm6_a
+ - pwm6_b
+ - pwm7_a
+ - pwm7_b
+ - pwm8_a
+ - pwm8_b
+ - pwm9_a
+ - pwm9_b
+ - pwm10_a
+ - pwm10_b
+ - pwm11_a
+ - pwm11_b
+ - rgmii0
+ - rmii0
+ - sdmmc0_1bit
+ - sdmmc0_4bit
+ - sdmmc0_cd
+ - sdmmc0_hs_sel
+ - sdmmc0_reset
+ - sdmmc0_wp
+ - sdmmc1_1bit
+ - sdmmc1_4bit
+ - sdmmc1_cd
+ - sdmmc1_hs_sel
+ - sdmmc1_reset
+ - sdmmc1_wp
+ - snand
+ - spi0
+ - spi1
+ - spi2
+ - spi3_a
+ - spi3_b
+ - spi3_c
+ - spi_slave_a
+ - spi_slave_b
+ - spi_slave_c
+ - spi_slave_d
+ - spi_slave_e
+ - spinor
+ - uart0
+ - uart1
+ - uart1_flow
+ - uart2_a
+ - uart2_b
+ - uart2_c
+ - uart2_flow_a
+ - uart2_flow_b
+ - uart3_a
+ - uart3_b
+ - uart3_flow_a
+ - uart3_flow_b
+ - uart4_a
+ - uart4_b
+ - uart4_flow_a
+ - uart4_flow_b
+ - vin_master_sync_a
+ - vin_master_sync_b
+ - vin_master_sync_c
+ - vin_master_sync_d
+ - vin_master_sync_e
+ - vsync0
+ - vsync1
+ - vsync2
+ - vsync3
+ - wdt_a
+ - wdt_b
+ - wdt_c
+ - wdt_d
+ - wdt_e
+ - wdt_f
+ minItems: 1
+ maxItems: 6
+ uniqueItems: true
+
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+
+ drive-strength:
+ enum: [3, 4, 5, 6, 7, 8, 9, 12]
+
+ required:
+ - function
+ - groups
+
+required:
+ - compatible
+ - reg
+ - ambarella,drive-strength-syscon
+ - ambarella,pull-syscon
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pinctrl: pinctrl@e4010000 {
+ compatible = "ambarella,cv75-pinctrl";
+ reg = <0xe4010000 0x1000>;
+ ambarella,drive-strength-syscon = <&rct>;
+ ambarella,pull-syscon = <&scratchpad>;
+
+ uart0-pins {
+ function = "uart0";
+ groups = "uart0";
+ bias-disable;
+ drive-strength = <8>;
+ };
+ };
--
2.34.1
next prev parent reply other threads:[~2026-08-18 10:32 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-18 10:31 [PATCH v5 00/12] Ambarella CV75 SoC minimal bring-up Long Zhao via B4 Relay
2026-08-18 10:31 ` [PATCH v5 01/12] dt-bindings: arm: add Ambarella CV75 platforms Long Zhao via B4 Relay
2026-08-18 10:35 ` sashiko-bot
2026-08-18 10:31 ` [PATCH v5 02/12] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Long Zhao via B4 Relay
2026-08-18 10:37 ` sashiko-bot
2026-08-18 19:27 ` Krzysztof Kozlowski
2026-08-19 9:21 ` zl020895
2026-08-18 10:31 ` [PATCH v5 03/12] dt-bindings: clock: add Ambarella CV75 RCT Long Zhao via B4 Relay
2026-08-18 10:36 ` sashiko-bot
2026-08-18 19:28 ` Krzysztof Kozlowski
2026-08-18 10:31 ` Long Zhao via B4 Relay [this message]
2026-08-18 10:39 ` [PATCH v5 04/12] dt-bindings: pinctrl: add Ambarella CV75 pinctrl sashiko-bot
2026-08-18 10:31 ` [PATCH v5 05/12] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-08-18 10:40 ` sashiko-bot
2026-08-19 7:47 ` Linus Walleij
2026-08-19 9:04 ` zl020895
2026-08-19 10:02 ` Linus Walleij
2026-08-18 10:31 ` [PATCH v5 06/12] dt-bindings: serial: add Ambarella CV75 UART Long Zhao via B4 Relay
2026-08-18 10:39 ` sashiko-bot
2026-08-19 7:32 ` Linus Walleij
2026-08-19 7:37 ` Krzysztof Kozlowski
2026-08-19 9:26 ` zl020895
2026-08-18 10:31 ` [PATCH v5 07/12] clk: ambarella: add CV75 CCU driver Long Zhao via B4 Relay
2026-08-18 10:46 ` sashiko-bot
2026-08-18 10:31 ` [PATCH v5 08/12] gpio: pl061: add Ambarella CV75 register layout variant Long Zhao via B4 Relay
2026-08-18 10:45 ` sashiko-bot
2026-08-18 14:11 ` Andy Shevchenko
[not found] ` <79f6dc8c.2c42c.1a018dadd29.Coremail.zl020895@163.com>
2026-08-19 7:27 ` Andy Shevchenko
2026-08-18 10:31 ` [PATCH v5 09/12] pinctrl: ambarella: add CV75 pin controller Long Zhao via B4 Relay
2026-08-18 10:48 ` sashiko-bot
2026-08-18 10:31 ` [PATCH v5 10/12] serial: 8250: add Ambarella UART driver Long Zhao via B4 Relay
2026-08-18 10:50 ` sashiko-bot
2026-08-18 14:17 ` Andy Shevchenko
[not found] ` <162c0385.2c076.1a018b82fa7.Coremail.zl020895@163.com>
2026-08-19 6:50 ` Andy Shevchenko
[not found] ` <4dfe3bbe.2c34f.1a018d297c3.Coremail.zl020895@163.com>
2026-08-19 7:34 ` Andy Shevchenko
2026-08-18 10:31 ` [PATCH v5 11/12] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Long Zhao via B4 Relay
2026-08-18 10:49 ` sashiko-bot
2026-08-18 10:31 ` [PATCH v5 12/12] MAINTAINERS: add ARM/AMBARELLA SoC support Long Zhao via B4 Relay
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