[PATCH v3 0/2] watchdog: Add Exynos5515 watchdog timer support

[PATCH v3 0/2] watchdog: Add Exynos5515 watchdog timer support

[Aiden Isik via B4 Relay]

Hi there,

This patchset adds support for the Exynos5515 SoC's watchdog timer
to the S3C2410 watchdog timer driver.

There is one checkpatch warning for this patchset:

> -------------------------------------------------------------------------
> Commit 8f4ec3a9b89b ("watchdog: s3c2410_wdt: Add exynos5515-wdt compatibl
> -------------------------------------------------------------------------
> WARNING: Avoid unnecessary line continuations
> #26: FILE: drivers/watchdog/s3c2410_wdt.c:240:
> +       .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \

Which seems to be erroneous: this line continuation is necessary
(and is done by every other existing entry).

Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
Changes in v3:
- Set reset_mask_inv to true
- Remove erroneous QUIRK_HAS_PMU_AUTO_DISABLE flag
- Link to v2: https://patch.msgid.link/20260818-for-next-lucky7-watchdog-v2-0-6743f479a47f@member.fsf.org

Changes in v2:
- Add samsung,cluster-index: false to documentation
- Remove SoC comment from documentation
- Correct signed-off-by tag in commits
- Link to v1: https://patch.msgid.link/20260817-for-next-lucky7-watchdog-v1-0-a14370e20b92@member.fsf.org

To: Wim Van Sebroeck <wim@linux-watchdog.org>
To: Guenter Roeck <linux@roeck-us.net>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Peter Griffin <peter.griffin@linaro.org>
To: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: linux-watchdog@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org

---
Aiden Isik (2):
      dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible
      watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

 .../devicetree/bindings/watchdog/samsung-wdt.yaml  | 23 +++++++++++++++++++++-
 drivers/watchdog/s3c2410_wdt.c                     | 12 +++++++++++
 2 files changed, 34 insertions(+), 1 deletion(-)
---
base-commit: acde40ba506aae78633e080b5704d33cf4bc13c6
change-id: 20260815-for-next-lucky7-watchdog-32bfb51191f1

Best regards,
--  
Aiden Isik <aidenisik@member.fsf.org>

[PATCH v3 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible

[Aiden Isik via B4 Relay]

From: Aiden Isik <aidenisik@member.fsf.org>

Add a dt-binding compatible for the Exynos5515 watchdog timer.

This watchdog requires a syscon phandle, and the cluster index should
*not* be specified, as that does not make sense on the Exynos5515 SoC
(due to it only having a single core cluster).

Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
 .../devicetree/bindings/watchdog/samsung-wdt.yaml  | 23 +++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
index 41aee1655b0c..a32c47831577 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
@@ -22,6 +22,7 @@ properties:
           - samsung,s3c6410-wdt                   # for S3C6410, S5PV210 and Exynos4
           - samsung,exynos5250-wdt                # for Exynos5250
           - samsung,exynos5420-wdt                # for Exynos5420
+          - samsung,exynos5515-wdt
           - samsung,exynos7-wdt                   # for Exynos7
           - samsung,exynos850-wdt                 # for Exynos850
           - samsung,exynos990-wdt                 # for Exynos990
@@ -57,7 +58,7 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:
       Phandle to the PMU system controller node (in case of Exynos5250,
-      Exynos5420, Exynos7, Exynos850, Exynos990 and gs101).
+      Exynos5420, Exynos5515, Exynos7, Exynos850, Exynos990 and gs101).
 
 required:
   - compatible
@@ -93,6 +94,26 @@ allOf:
         - samsung,cluster-index
         - samsung,syscon-phandle
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - samsung,exynos5515-wdt
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Bus clock, used for register interface
+            - description: Source clock (driving watchdog counter)
+        clock-names:
+          items:
+            - const: watchdog
+            - const: watchdog_src
+        samsung,cluster-index: false
+      required:
+        - samsung,syscon-phandle
+
   - if:
       properties:
         compatible:

-- 
2.54.0

[PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

[Aiden Isik via B4 Relay]

From: Aiden Isik <aidenisik@member.fsf.org>

Add driver data for the Exynos5515 SoC's watchdog timer.

Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
 drivers/watchdog/s3c2410_wdt.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index e31f93db0509..5592f25fe6c8 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -232,6 +232,16 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
 		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
 };
 
+static const struct s3c2410_wdt_variant drv_data_exynos5515 = {
+	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
+	.mask_bit = 2,
+	.mask_reset_inv = true,
+	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
+	.rst_stat_bit = 24,
+	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
+		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_DBGACK_BIT,
+};
+
 static const struct s3c2410_wdt_variant drv_data_exynos7 = {
 	.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
 	.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
@@ -379,6 +389,8 @@ static const struct of_device_id s3c2410_wdt_match[] = {
 	  .data = &drv_data_exynos5250 },
 	{ .compatible = "samsung,exynos5420-wdt",
 	  .data = &drv_data_exynos5420 },
+	{ .compatible = "samsung,exynos5515-wdt",
+	  .data = &drv_data_exynos5515 },
 	{ .compatible = "samsung,exynos7-wdt",
 	  .data = &drv_data_exynos7 },
 	{ .compatible = "samsung,exynos850-wdt",

-- 
2.54.0

Re: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing PMU counter enable configuration for Exynos5515 watchdog.
--

--- Patch [2]: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data ---
commit 9ce360e3c933b7447ba5da9ba1b7ae3fee989703
Author: Aiden Isik <aidenisik@member.fsf.org>

watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data
    
This commit adds driver data for the Exynos5515 SoC's watchdog timer.

> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index e31f93db05096..5592f25fe6c83 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -232,6 +232,16 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
>  		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
>  };
>  
> +static const struct s3c2410_wdt_variant drv_data_exynos5515 = {
> +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = 24,
> +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
> +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_DBGACK_BIT,
> +};

[Severity: Medium]
Does the Exynos5515 PMU require explicit counter enablement like other recent
Exynos SoCs?

Other variants in this driver (like Exynos850, AutoV920, and GS101) that use
the NONCPU_INT_EN PMU registers also pair it with a NONCPU_OUT register and
the QUIRK_HAS_PMU_CNT_EN flag to ensure the watchdog counter ticks.

If the Exynos5515 hardware works similarly, omitting cnt_en_reg, cnt_en_bit,
and QUIRK_HAS_PMU_CNT_EN here might leave the counter disabled and the
watchdog silently non-functional. Could you confirm if this variant needs the
counter enable logic?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260818-for-next-lucky7-watchdog-v3-0-2912bd122c57@member.fsf.org?part=2

Re: [PATCH v3 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The new `samsung,exynos5515-wdt` conditional block may incorrectly enforce a 2-clock constraint, potentially violating the subsystem generation grouping rule.
--

--- Patch [1]: [PATCH v3 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible ---
commit 751ef37a6e709e26029d210213d732f6299f833b
Author: Aiden Isik <aidenisik@member.fsf.org>

dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible
    
Add a dt-binding compatible for the Exynos5515 watchdog timer.
    
This watchdog requires a syscon phandle, and the cluster index should
*not* be specified, as that does not make sense on the Exynos5515 SoC
(due to it only having a single core cluster).

> diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> index 41aee1655b0c2..a32c478315779 100644
> --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml

[ ... ]

> @@ -93,6 +94,26 @@ allOf:
>          - samsung,cluster-index
>          - samsung,syscon-phandle
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - samsung,exynos5515-wdt
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: Bus clock, used for register interface
> +            - description: Source clock (driving watchdog counter)
> +        clock-names:
> +          items:
> +            - const: watchdog
> +            - const: watchdog_src

[Severity: Medium]
Does the Exynos 5515 hardware actually require two clocks?

Other Exynos 5 hardware, like the exynos5250 and exynos5420, typically
use a single clock constraint.

If the Exynos 5515 only has a single clock, this two-clock constraint will
unintentionally force device tree authors to provide a non-existent second
clock to pass schema validation.

> +        samsung,cluster-index: false
> +      required:
> +        - samsung,syscon-phandle
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260818-for-next-lucky7-watchdog-v3-0-2912bd122c57@member.fsf.org?part=1

Re: [PATCH v3 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible

[Aiden Isik]

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] The new `samsung,exynos5515-wdt` conditional block may incorrectly enforce a 2-clock constraint, potentially violating the subsystem generation grouping rule.
> --
>
> --- Patch [1]: [PATCH v3 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible ---
> commit 751ef37a6e709e26029d210213d732f6299f833b
> Author: Aiden Isik <aidenisik@member.fsf.org>
>
> dt-bindings: watchdog: samsung-wdt: Add exynos5515-wdt compatible
>
> Add a dt-binding compatible for the Exynos5515 watchdog timer.
>
> This watchdog requires a syscon phandle, and the cluster index should
> *not* be specified, as that does not make sense on the Exynos5515 SoC
> (due to it only having a single core cluster).
>
> > diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> > index 41aee1655b0c2..a32c478315779 100644
> > --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> > +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
>
> [ ... ]
>
> > @@ -93,6 +94,26 @@ allOf:
> >          - samsung,cluster-index
> >          - samsung,syscon-phandle
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - samsung,exynos5515-wdt
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: Bus clock, used for register interface
> > +            - description: Source clock (driving watchdog counter)
> > +        clock-names:
> > +          items:
> > +            - const: watchdog
> > +            - const: watchdog_src
>
> [Severity: Medium]
> Does the Exynos 5515 hardware actually require two clocks?
>
> Other Exynos 5 hardware, like the exynos5250 and exynos5420, typically
> use a single clock constraint.
>
> If the Exynos 5515 only has a single clock, this two-clock constraint will
> unintentionally force device tree authors to provide a non-existent second
> clock to pass schema validation.

Exynos5515 is more similar to Exynos990 and Exynos2200 than Exynos5.
Two clocks is correct.

>
> > +        samsung,cluster-index: false
> > +      required:
> > +        - samsung,syscon-phandle
> > +
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260818-for-next-lucky7-watchdog-v3-0-2912bd122c57@member.fsf.org?part=1
>

Re: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

[Aiden Isik]

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] Missing PMU counter enable configuration for Exynos5515 watchdog.
> --
> 
> --- Patch [2]: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data ---
> commit 9ce360e3c933b7447ba5da9ba1b7ae3fee989703
> Author: Aiden Isik <aidenisik@member.fsf.org>
> 
> watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data
> 
> This commit adds driver data for the Exynos5515 SoC's watchdog timer.
> 
> > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> > index e31f93db05096..5592f25fe6c83 100644
> > --- a/drivers/watchdog/s3c2410_wdt.c
> > +++ b/drivers/watchdog/s3c2410_wdt.c
> > @@ -232,6 +232,16 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
> >  		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
> >  };
> >
> > +static const struct s3c2410_wdt_variant drv_data_exynos5515 = {
> > +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> > +	.mask_bit = 2,
> > +	.mask_reset_inv = true,
> > +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> > +	.rst_stat_bit = 24,
> > +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
> > +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_DBGACK_BIT,
> > +};
> 
> [Severity: Medium]
> Does the Exynos5515 PMU require explicit counter enablement like other recent
> Exynos SoCs?
> 
> Other variants in this driver (like Exynos850, AutoV920, and GS101) that use
> the NONCPU_INT_EN PMU registers also pair it with a NONCPU_OUT register and
> the QUIRK_HAS_PMU_CNT_EN flag to ensure the watchdog counter ticks.
> 
> If the Exynos5515 hardware works similarly, omitting cnt_en_reg, cnt_en_bit,
> and QUIRK_HAS_PMU_CNT_EN here might leave the counter disabled and the
> watchdog silently non-functional. Could you confirm if this variant needs the
> counter enable logic?

Exynos5515 does not require this.

Downstream on GS101, as an example, has this struct member set:

> pmu_count_en_func

This is not set downstream for Exynos5515, so it is not used for
Exynos5515.

> 
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260818-for-next-lucky7-watchdog-v3-0-2912bd122c57@member.fsf.org?part=2
>

Re: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

[Guenter Roeck]

On 8/18/26 11:33, Aiden Isik wrote:
>> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>> - [Medium] Missing PMU counter enable configuration for Exynos5515 watchdog.
>> --
>>
>> --- Patch [2]: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data ---
>> commit 9ce360e3c933b7447ba5da9ba1b7ae3fee989703
>> Author: Aiden Isik <aidenisik@member.fsf.org>
>>
>> watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data
>>
>> This commit adds driver data for the Exynos5515 SoC's watchdog timer.
>>
>>> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
>>> index e31f93db05096..5592f25fe6c83 100644
>>> --- a/drivers/watchdog/s3c2410_wdt.c
>>> +++ b/drivers/watchdog/s3c2410_wdt.c
>>> @@ -232,6 +232,16 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
>>>   		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
>>>   };
>>>
>>> +static const struct s3c2410_wdt_variant drv_data_exynos5515 = {
>>> +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
>>> +	.mask_bit = 2,
>>> +	.mask_reset_inv = true,
>>> +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
>>> +	.rst_stat_bit = 24,
>>> +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
>>> +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_DBGACK_BIT,
>>> +};
>>
>> [Severity: Medium]
>> Does the Exynos5515 PMU require explicit counter enablement like other recent
>> Exynos SoCs?
>>
>> Other variants in this driver (like Exynos850, AutoV920, and GS101) that use
>> the NONCPU_INT_EN PMU registers also pair it with a NONCPU_OUT register and
>> the QUIRK_HAS_PMU_CNT_EN flag to ensure the watchdog counter ticks.
>>
>> If the Exynos5515 hardware works similarly, omitting cnt_en_reg, cnt_en_bit,
>> and QUIRK_HAS_PMU_CNT_EN here might leave the counter disabled and the
>> watchdog silently non-functional. Could you confirm if this variant needs the
>> counter enable logic?
> 
> Exynos5515 does not require this.
> 
> Downstream on GS101, as an example, has this struct member set:
> 
>> pmu_count_en_func
> 
> This is not set downstream for Exynos5515, so it is not used for
> Exynos5515.
> 

You keep talking about "downstream". What is that ?

Guenter

Re: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

[Aiden Isik]

Hi Guenter,

> On 8/18/26 11:33, Aiden Isik wrote:
> >> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> >> - [Medium] Missing PMU counter enable configuration for Exynos5515 watchdog.
> >> --
> >>
> >> --- Patch [2]: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data ---
> >> commit 9ce360e3c933b7447ba5da9ba1b7ae3fee989703
> >> Author: Aiden Isik <aidenisik@member.fsf.org>
> >>
> >> watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data
> >>
> >> This commit adds driver data for the Exynos5515 SoC's watchdog timer.
> >>
> >>> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> >>> index e31f93db05096..5592f25fe6c83 100644
> >>> --- a/drivers/watchdog/s3c2410_wdt.c
> >>> +++ b/drivers/watchdog/s3c2410_wdt.c
> >>> @@ -232,6 +232,16 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
> >>>   		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
> >>>   };
> >>>
> >>> +static const struct s3c2410_wdt_variant drv_data_exynos5515 = {
> >>> +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> >>> +	.mask_bit = 2,
> >>> +	.mask_reset_inv = true,
> >>> +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> >>> +	.rst_stat_bit = 24,
> >>> +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
> >>> +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_DBGACK_BIT,
> >>> +};
> >>
> >> [Severity: Medium]
> >> Does the Exynos5515 PMU require explicit counter enablement like other recent
> >> Exynos SoCs?
> >>
> >> Other variants in this driver (like Exynos850, AutoV920, and GS101) that use
> >> the NONCPU_INT_EN PMU registers also pair it with a NONCPU_OUT register and
> >> the QUIRK_HAS_PMU_CNT_EN flag to ensure the watchdog counter ticks.
> >>
> >> If the Exynos5515 hardware works similarly, omitting cnt_en_reg, cnt_en_bit,
> >> and QUIRK_HAS_PMU_CNT_EN here might leave the counter disabled and the
> >> watchdog silently non-functional. Could you confirm if this variant needs the
> >> counter enable logic?
> >
> > Exynos5515 does not require this.
> >
> > Downstream on GS101, as an example, has this struct member set:
> >
> >> pmu_count_en_func
> >
> > This is not set downstream for Exynos5515, so it is not used for
> > Exynos5515.
> >
> 
> You keep talking about "downstream". What is that ?

By "downstream" I am referring specifically to Samsung's Linux kernel
fork for Exynos5515.

I host a copy here: https://github.com/Aiden-Isik/linux-android-lucky7

Also in this message I refer to Google's GS101 kernel fork, which can
be found here:
https://github.com/LineageOS/android_kernel_google_gs101

> 
> Guenter
> 
> 

Kind regards,
- Aiden Isik

Re: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

[Guenter Roeck]

On 8/18/26 12:35, Aiden Isik wrote:
> Hi Guenter,
> 
>> On 8/18/26 11:33, Aiden Isik wrote:
>>>> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>>>> - [Medium] Missing PMU counter enable configuration for Exynos5515 watchdog.
>>>> --
>>>>
>>>> --- Patch [2]: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data ---
>>>> commit 9ce360e3c933b7447ba5da9ba1b7ae3fee989703
>>>> Author: Aiden Isik <aidenisik@member.fsf.org>
>>>>
>>>> watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data
>>>>
>>>> This commit adds driver data for the Exynos5515 SoC's watchdog timer.
>>>>
>>>>> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
>>>>> index e31f93db05096..5592f25fe6c83 100644
>>>>> --- a/drivers/watchdog/s3c2410_wdt.c
>>>>> +++ b/drivers/watchdog/s3c2410_wdt.c
>>>>> @@ -232,6 +232,16 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
>>>>>    		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
>>>>>    };
>>>>>
>>>>> +static const struct s3c2410_wdt_variant drv_data_exynos5515 = {
>>>>> +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
>>>>> +	.mask_bit = 2,
>>>>> +	.mask_reset_inv = true,
>>>>> +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
>>>>> +	.rst_stat_bit = 24,
>>>>> +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
>>>>> +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_DBGACK_BIT,
>>>>> +};
>>>>
>>>> [Severity: Medium]
>>>> Does the Exynos5515 PMU require explicit counter enablement like other recent
>>>> Exynos SoCs?
>>>>
>>>> Other variants in this driver (like Exynos850, AutoV920, and GS101) that use
>>>> the NONCPU_INT_EN PMU registers also pair it with a NONCPU_OUT register and
>>>> the QUIRK_HAS_PMU_CNT_EN flag to ensure the watchdog counter ticks.
>>>>
>>>> If the Exynos5515 hardware works similarly, omitting cnt_en_reg, cnt_en_bit,
>>>> and QUIRK_HAS_PMU_CNT_EN here might leave the counter disabled and the
>>>> watchdog silently non-functional. Could you confirm if this variant needs the
>>>> counter enable logic?
>>>
>>> Exynos5515 does not require this.
>>>
>>> Downstream on GS101, as an example, has this struct member set:
>>>
>>>> pmu_count_en_func
>>>
>>> This is not set downstream for Exynos5515, so it is not used for
>>> Exynos5515.
>>>
>>
>> You keep talking about "downstream". What is that ?
> 
> By "downstream" I am referring specifically to Samsung's Linux kernel
> fork for Exynos5515.
> 
> I host a copy here: https://github.com/Aiden-Isik/linux-android-lucky7
> 
> Also in this message I refer to Google's GS101 kernel fork, which can
> be found here:
> https://github.com/LineageOS/android_kernel_google_gs101
> 

Both are completely irrelevant for the upstream kernel. I am most definitely
not going to look into that code. If there is anything relevant - such as
the comment you pointed to earlier - you'll need to provide that as independent
comment(s), not just refer to some downstream code as explanation. The
explanation needs to be provided in the _upstream_ kernel code.

Guenter

>>
>> Guenter
>>
>>
> 
> Kind regards,
> - Aiden Isik

Re: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data

[Aiden Isik]

Hi Guenter,

> On 8/18/26 12:35, Aiden Isik wrote:
> > Hi Guenter,
> >
> >> On 8/18/26 11:33, Aiden Isik wrote:
> >>>> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> >>>> - [Medium] Missing PMU counter enable configuration for Exynos5515 watchdog.
> >>>> --
> >>>>
> >>>> --- Patch [2]: [PATCH v3 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data ---
> >>>> commit 9ce360e3c933b7447ba5da9ba1b7ae3fee989703
> >>>> Author: Aiden Isik <aidenisik@member.fsf.org>
> >>>>
> >>>> watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data
> >>>>
> >>>> This commit adds driver data for the Exynos5515 SoC's watchdog timer.
> >>>>
> >>>>> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> >>>>> index e31f93db05096..5592f25fe6c83 100644
> >>>>> --- a/drivers/watchdog/s3c2410_wdt.c
> >>>>> +++ b/drivers/watchdog/s3c2410_wdt.c
> >>>>> @@ -232,6 +232,16 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
> >>>>>    		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
> >>>>>    };
> >>>>>
> >>>>> +static const struct s3c2410_wdt_variant drv_data_exynos5515 = {
> >>>>> +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> >>>>> +	.mask_bit = 2,
> >>>>> +	.mask_reset_inv = true,
> >>>>> +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> >>>>> +	.rst_stat_bit = 24,
> >>>>> +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
> >>>>> +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_DBGACK_BIT,
> >>>>> +};
> >>>>
> >>>> [Severity: Medium]
> >>>> Does the Exynos5515 PMU require explicit counter enablement like other recent
> >>>> Exynos SoCs?
> >>>>
> >>>> Other variants in this driver (like Exynos850, AutoV920, and GS101) that use
> >>>> the NONCPU_INT_EN PMU registers also pair it with a NONCPU_OUT register and
> >>>> the QUIRK_HAS_PMU_CNT_EN flag to ensure the watchdog counter ticks.
> >>>>
> >>>> If the Exynos5515 hardware works similarly, omitting cnt_en_reg, cnt_en_bit,
> >>>> and QUIRK_HAS_PMU_CNT_EN here might leave the counter disabled and the
> >>>> watchdog silently non-functional. Could you confirm if this variant needs the
> >>>> counter enable logic?
> >>>
> >>> Exynos5515 does not require this.
> >>>
> >>> Downstream on GS101, as an example, has this struct member set:
> >>>
> >>>> pmu_count_en_func
> >>>
> >>> This is not set downstream for Exynos5515, so it is not used for
> >>> Exynos5515.
> >>>
> >>
> >> You keep talking about "downstream". What is that ?
> >
> > By "downstream" I am referring specifically to Samsung's Linux kernel
> > fork for Exynos5515.
> >
> > I host a copy here: https://github.com/Aiden-Isik/linux-android-lucky7
> >
> > Also in this message I refer to Google's GS101 kernel fork, which can
> > be found here:
> > https://github.com/LineageOS/android_kernel_google_gs101
> >
> 
> Both are completely irrelevant for the upstream kernel. I am most definitely
> not going to look into that code. If there is anything relevant - such as
> the comment you pointed to earlier - you'll need to provide that as independent
> comment(s), not just refer to some downstream code as explanation. The
> explanation needs to be provided in the _upstream_ kernel code.
> 

There's not really any explanation for it other than "that is the way it is".
Samsung designed the Exynos5515 watchdog timer to not have that quirk,
I read the downstream code and learnt that fact, so we don't enable
that quirk.

> Guenter
> 
> >>
> >> Guenter
> >>
> >>
> >
> > Kind regards,
> > - Aiden Isik
> 
> 

Kind regards,
- Aiden Isik