[PATCH v3 0/4] arm64: dts: qcom: Describe the PCIe M.2 Key E connector for Monaco EVK

[PATCH v3 0/4] arm64: dts: qcom: Describe the PCIe M.2 Key E connector for Monaco EVK

[Wei Deng]

Add DT support for the PCIe M.2 Mechanical Key E connector on the
Monaco EVK, following the same pattern as the lemans-evk series
(already in linux-next, commits 67f06acf/a6d4bb0a).

Patch 1/4 adds 'compatible = "pciclass,0604"' to the pcieport0 node in
monaco.dtsi, required for downstream DT nodes to be matched to PCI
devices.

Patch 2/4 adds empty labeled endpoints (pcieport0_ep, uart2_ep) to
pcieport0 and uart2 in monaco.dtsi as graph anchors.

Patch 3/4 describes the connector-3 node in monaco-evk.dts, wires the
endpoints via remote-endpoint overrides, adds the vreg_wcn_3p3
regulator, and adds the serial1 = &uart2 alias for BT serdev
enumeration.

Patch 4/4 moves the graph port/endpoint anchors from monaco.dtsi to
monaco-evk.dts. This ensures of_graph_is_present() only returns true
for boards that have an M.2 Key E connector present, preventing
unintended pwrseq probe on boards with soldered wireless chips
(e.g. qcs8300-ride).

This series is based on next-20260726.

Changes in v3:
- Drop vreg_dcin_12v from connector node; the 12V DC input is not
  software-controllable (Konrad)
- Add patch 4/4: move graph port/endpoint anchors from monaco.dtsi to
  monaco-evk.dts, so of_graph_is_present() only returns true on boards
  with an M.2 Key E connector; note that patch 2/4 (the anchor additions
  in monaco.dtsi) is based on a pending upstream series not yet merged:
  https://lore.kernel.org/all/20260720-monza-wireless-v5-1-69ec6743543c@oss.qualcomm.com/
- Link to v2: https://lore.kernel.org/r/20260729-b4-monaco-evk-m2-v1-v2-0-0548e1dab760@oss.qualcomm.com

Changes in v2:
- Move PCIe Root Port and UART2 graph port/endpoint declarations from
  monaco-evk.dts into monaco.dtsi, per Konrad's suggestion. The SoC
  DTSI now defines empty labeled endpoints (pcieport0_ep, uart2_ep) as
  graph anchors, and monaco-evk.dts wires them via remote-endpoint
  overrides. Splits the old patch 2/2 into two patches (new patch 2/3
  for the anchors, patch 3/3 for the EVK board wiring).
- Patch 1/3 unchanged, carries Konrad's Reviewed-by from v1.
- Dropped Dmitry's Reviewed-by on the EVK patch since the port/endpoint
  structure changed; open to re-review.
- Link to v1: https://lore.kernel.org/all/20260727-b4-monaco-evk-m2-v1-v1-0-5429cce68599@oss.qualcomm.com/

---
Wei Deng (4):
      arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port
      arm64: dts: qcom: monaco: Add graph port/endpoint anchors to pcieport0 and uart2
      arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector
      arm64: dts: qcom: monaco{,-evk}: Move graph port/endpoint anchors to board file

 arch/arm64/boot/dts/qcom/monaco-evk.dts | 60 +++++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/monaco.dtsi    |  1 +
 2 files changed, 61 insertions(+)
---
base-commit: 80489b8b7c62068b5223af10ead175367dcd127d
change-id: 20260727-b4-monaco-evk-m2-v1-dd56eb997378

Best regards,
-- 
Wei Deng <wei.deng@oss.qualcomm.com>

[PATCH v3 1/4] arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port

[Wei Deng]

Add 'compatible = "pciclass,0604"' to the pcieport0 node in monaco.dtsi
to allow the PCI subsystem to associate the DT node with the PCI-to-PCI
bridge device. This is required for downstream DT nodes (such as M.2
connectors described as graph endpoints of the Root Port) to be matched
to PCI devices.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 64fc0d592282..438ccf6eba64 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2393,6 +2393,7 @@ opp-32000000 {
 			};
 
 			pcieport0: pcie@0 {
+				compatible = "pciclass,0604";
 				device_type = "pci";
 				reg = <0x0 0x0 0x0 0x0 0x0>;
 				bus-range = <0x01 0xff>;

-- 
2.34.1

Re: [PATCH v3 1/4] arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] This problem wasn't introduced by this patch, but the patch provides an incomplete fix. It adds `compatible = "pciclass,0604";` to `pcieport0` to enable PCI-to-PCI bridge matching, but fails to apply the same required fix to the identical `pcieport1` node in the same file.
--

--- Patch [1]: [PATCH v3 1/4] arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port ---
commit aa27523e9b0a54b6db3c28da2c6526d7f13eeef7
Author: Wei Deng <wei.deng@oss.qualcomm.com>

arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port

This patch adds the "pciclass,0604" compatible string to the pcieport0 node
in monaco.dtsi. This enables the PCI subsystem to properly associate the DT
node with the PCI-to-PCI bridge device, allowing downstream DT nodes to be
matched.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index e4c8466f941bd..44526f4d85870 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2413,6 +2413,7 @@ opp-32000000 {
>  			};
>  
>  			pcieport0: pcie@0 {
> +				compatible = "pciclass,0604";
>  				device_type = "pci";
>  				reg = <0x0 0x0 0x0 0x0 0x0>;
>  				bus-range = <0x01 0xff>;

[Severity: High]
This isn't a bug introduced by this patch, but does this provide an incomplete
fix?

Looking further down in arch/arm64/boot/dts/qcom/monaco.dtsi, there is a
second PCIe Root Port that is missing this compatible string:

			pcieport1: pcie@0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;
				...

Without the "pciclass,0604" property here, the PCI subsystem cannot associate
the DT node for pcieport1 with the physical PCI-to-PCI bridge device. This
prevents downstream endpoints from being assigned their respective of_node,
breaking the binding of PCI power control drivers (e.g., pci-pwrctrl-pwrseq)
and leaving the devices unusable.

Should this compatible string be added to pcieport1 as well?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260819-b4-monaco-evk-m2-v1-v3-0-988145ef65cd@oss.qualcomm.com?part=1

[PATCH v3 2/4] arm64: dts: qcom: monaco: Add graph port/endpoint anchors to pcieport0 and uart2

[Wei Deng]

Add empty graph port/endpoint nodes to pcieport0 and uart2 in monaco.dtsi
so that board files can reference the endpoint labels (pcieport0_ep,
uart2_ep) to describe connections to M.2 Key E connectors via
remote-endpoint overrides.

Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 438ccf6eba64..b17d41059e7c 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -1184,6 +1184,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 				power-domains = <&rpmhpd RPMHPD_CX>;
 				operating-points-v2 = <&qup_opp_table>;
 				status = "disabled";
+
+				port {
+					uart2_ep: endpoint {};
+				};
 			};
 
 			i2c3: i2c@98c000 {
@@ -2402,6 +2406,10 @@ pcieport0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 				phys = <&pcie0_phy>;
+
+				port {
+					pcieport0_ep: endpoint {};
+				};
 			};
 		};
 

-- 
2.34.1

[PATCH v3 3/4] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

[Wei Deng]

The monaco EVK has a PCIe M.2 Mechanical Key E connector to connect
wireless connectivity cards over PCIe and UART interfaces. Hence,
describe the connector node and link it with the PCIe 0 Root Port and
UART2 nodes through graph port/endpoint.

The connector's 3.3V supply is described as a fixed always-on regulator
(vreg_wcn_3p3), which is required by the pcie-m2-e-connector binding.

Also add the serial1 = &uart2 alias, which is required for the
Bluetooth serdev device to be enumerated on the UART2 interface.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco-evk.dts | 56 +++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index 9d17ef7d2caf..5930ddb3b4b1 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -21,6 +21,7 @@ aliases {
 		ethernet0 = &ethernet0;
 		i2c1 = &i2c1;
 		serial0 = &uart7;
+		serial1 = &uart2;
 		serial2 = &uart6;
 	};
 
@@ -47,6 +48,38 @@ usb2_con_hs_ep: endpoint {
 		};
 	};
 
+	connector-3 {
+		compatible = "pcie-m2-e-connector";
+		vpcie3v3-supply = <&vreg_wcn_3p3>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				m2_e_pcie_ep: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&pcieport0_ep>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				m2_e_uart_ep: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&uart2_ep>;
+				};
+			};
+		};
+	};
+
 	dmic: audio-codec-0 {
 		compatible = "dmic-codec";
 		#sound-dai-cells = <0>;
@@ -91,6 +124,17 @@ usb2_vbus: regulator-usb2-vbus {
 		enable-active-high;
 	};
 
+	vreg_wcn_3p3: regulator-wcn-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
 	sound {
 		compatible = "qcom,qcs8275-sndcard";
 		model = "MONACO-EVK";
@@ -646,6 +690,10 @@ &pcieport0 {
 	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 };
 
+&pcieport0_ep {
+	remote-endpoint = <&m2_e_pcie_ep>;
+};
+
 &pcieport1 {
 	reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
 	wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
@@ -923,3 +971,11 @@ &usb_2_hsphy {
 
 	status = "okay";
 };
+
+&uart2 {
+	status = "okay";
+};
+
+&uart2_ep {
+	remote-endpoint = <&m2_e_uart_ep>;
+};

-- 
2.34.1

Re: [PATCH v3 3/4] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Node overrides are not sorted alphabetically.
--

--- Patch [3]: [PATCH v3 3/4] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector ---
commit 208b6f2eef3b23e678fa76e3866767bc52da9a8e
Author: Wei Deng <wei.deng@oss.qualcomm.com>

arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

The monaco EVK has a PCIe M.2 Mechanical Key E connector to connect
wireless connectivity cards over PCIe and UART interfaces. Hence,
describe the connector node and link it with the PCIe 0 Root Port and
UART2 nodes through graph port/endpoint.

> diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
> index 9d17ef7d2caf1..5930ddb3b4b18 100644
> --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts

[ ... ]

> @@ -923,3 +971,11 @@ &usb_2_hsphy {
>  
>  	status = "okay";
>  };
> +
> +&uart2 {
> +	status = "okay";
> +};
> +
> +&uart2_ep {
> +	remote-endpoint = <&m2_e_uart_ep>;
> +};

[Severity: Low]
Are these node overrides out of alphabetical order?

They appear to be appended to the end of the file after &usb_2_hsphy, rather
than sorted alphabetically alongside the other node overrides.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260819-b4-monaco-evk-m2-v1-v3-0-988145ef65cd@oss.qualcomm.com?part=3

[PATCH v3 4/4] arm64: dts: qcom: monaco{,-evk}: Move graph port/endpoint anchors to board file

[Wei Deng]

of_graph_is_present() only checks for the presence of a 'port' child
node, not whether remote-endpoint is actually connected. Adding empty
port anchor nodes to monaco.dtsi caused hci_qca to enter the M.2
pwrseq probe path on all monaco-based boards, including qcs8300-ride
which has a soldered WCN6855 and no M.2 Key E connector. This broke
BT initialization on qcs8300-ride.

Fix this by moving the port/endpoint nodes from monaco.dtsi into the
monaco-evk.dts board file where the M.2 connector is actually present,
so that of_graph_is_present() only returns true for boards that have
an M.2 Key E connector described.

Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco-evk.dts | 16 ++++++++++------
 arch/arm64/boot/dts/qcom/monaco.dtsi    |  8 --------
 2 files changed, 10 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index 5930ddb3b4b1..5aae3d8c66a1 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -688,10 +688,12 @@ &pcie1_phy {
 &pcieport0 {
 	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
 	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-};
 
-&pcieport0_ep {
-	remote-endpoint = <&m2_e_pcie_ep>;
+	port {
+		pcieport0_ep: endpoint {
+			remote-endpoint = <&m2_e_pcie_ep>;
+		};
+	};
 };
 
 &pcieport1 {
@@ -974,8 +976,10 @@ &usb_2_hsphy {
 
 &uart2 {
 	status = "okay";
-};
 
-&uart2_ep {
-	remote-endpoint = <&m2_e_uart_ep>;
+	port {
+		uart2_ep: endpoint {
+			remote-endpoint = <&m2_e_uart_ep>;
+		};
+	};
 };
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index b17d41059e7c..438ccf6eba64 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -1184,10 +1184,6 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 				power-domains = <&rpmhpd RPMHPD_CX>;
 				operating-points-v2 = <&qup_opp_table>;
 				status = "disabled";
-
-				port {
-					uart2_ep: endpoint {};
-				};
 			};
 
 			i2c3: i2c@98c000 {
@@ -2406,10 +2402,6 @@ pcieport0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 				phys = <&pcie0_phy>;
-
-				port {
-					pcieport0_ep: endpoint {};
-				};
 			};
 		};
 

-- 
2.34.1

Re: [PATCH v3 0/4] arm64: dts: qcom: Describe the PCIe M.2 Key E connector for Monaco EVK

[Wei Deng]

Hi Konrad,

On Wed, 19 Aug 2026 19:27:31 +0530, Wei Deng wrote:
> Patch 4/4 moves the graph port/endpoint anchors from monaco.dtsi to
> monaco-evk.dts. This ensures of_graph_is_present() only returns true
> for boards that have an M.2 Key E connector present, preventing
> unintended pwrseq probe on boards with soldered wireless chips
> (e.g. qcs8300-ride).

I reached out to Manivannan to ask whether it would be acceptable to
change the M.2 detection in hci_qca.c from of_graph_is_present() to
of_graph_get_remote_endpoint(). His reply [1]:

> This means, the dummy port/endpoint node will always be present even
> when the M.2 connector is not used. I don't see a compelling reason
> to do so.
>
> - Mani

Given that feedback, the DTSI anchor approach (which you originally
suggested and reviewed) cannot proceed without the hci_qca.c detection
change, and that change is not something Mani finds compelling.

I'm therefore planning to drop the DTSI anchor patch in v4 and go with
board-file-only port/endpoint nodes. The series would shrink to 3 patches
and no DTSI anchors would be added.

Could you confirm whether this approach is acceptable before I send v4?

[1] https://lore.kernel.org/all/isbrpaztfrgwfcleujrn4w26cshbi2mgn57tbh5bubvsegn6lc@jh3ab6htvd24/

--
Best Regards,
Wei Deng