Re: [PATCH v4 1/2] dt-bindings: mmc: cdns,sdhci: Add CQE support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `else` block for non-Elba platforms lacks explicit `maxItems: 2` constraints for `reg` and `reg-names`, creating a validation loophole that allows non-Elba platforms to define an invalid third register.
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--- Patch [1]: [PATCH v4 1/2] dt-bindings: mmc: cdns,sdhci: Add CQE support ---
commit 48a4d35cce2e12157d9c52de4ba805fd4e404597
Author: Rohan Joshi <rohan1sj@cadence.com>

dt-bindings: mmc: cdns,sdhci: Add CQE support

This commit adds an optional cqhci named resource to map the CQE register
space. It updates the amd,pensando-elba platform to include this resource
while maintaining compatibility for platforms without the CQE block.

> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml

[ ... ]

> @@ -131,13 +138,27 @@ allOf:
>      then:
>        properties:
>          reg:
> +          minItems: 2
>            items:
>              - description: Host controller registers
>              - description: Elba byte-lane enable register for writes
> +            - description: CQE (Command Queuing Engine) registers (optional)
> +        reg-names:
> +          minItems: 2
> +          items:
> +            - const: hc
> +            - const: bctl
> +            - const: cqhci
>      else:
>        properties:
>          reg:
> -          maxItems: 1
> +          items:
> +            - description: Host Controller registers
> +            - description: CQE (Command Queuing Engine) registers (optional)
> +        reg-names:
> +          items:
> +            - const: hc
> +            - const: cqhci

[Severity: Low]
Since the top-level schema was updated to permit up to 3 items for reg, does
omitting an explicit maxItems limit in this else block allow non-Elba
platforms to define an invalid third register and silently pass validation?

In dt-schema, an items list inside an if/then/else block does not restrict
the overall length unless maxItems is explicitly defined.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825-cdns_sdhci_cqe-support-v4-0-e9f72e338373@cadence.com?part=1